Search results for "simultaneous scheduling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh	Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
2	Pradeep Prabhakaran, Prithviraj Banerjee	Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis.	VLSI Design	1998	DBLP DOI BibTeX RDF	timing driven synthesis, High-level synthesis, floorplanning
2	Ireneusz Karkowski	Architectural synthesis with possibilistic programming.	HICSS	1995	DBLP DOI BibTeX RDF	possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory
2	Neerav Berry, Barry M. Pangrle	SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Hariharan Sankaran, Srinivas Katkoori	Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Donatas Elvikis, Horst W. Hamacher, Marcel T. Kalsch	Simultaneous scheduling and location (ScheLoc): the planar ScheLoc makespan problem.	J. Scheduling	2009	DBLP DOI BibTeX RDF	Global optimization, Scheduling theory, Location theory
1	Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan	Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Hariharan Sankaran, Srinivas Katkoori	Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Yi Sun, James Nutaro	Performance Improvement Using Parallel Simulation Protocol and Time Warp for DEVS Based Applications.	DS-RT	2008	DBLP DOI BibTeX RDF
1	Eddy Caron, Frédéric Desprez, Gaël Le Mahec	Parallelization and Distribution Strategies of Large Bioinformatics Requests over the Grid.	ICA3PP	2008	DBLP DOI BibTeX RDF
1	Dongxin Wen, Ling Wang, Yingtao Jiang, Henry Selvaraj, Xiao-Zong Yang	Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages.	I. J. Comput. Appl.	2007	DBLP BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Janina A. Brenner, Sándor P. Fekete, Jan van der Veen	Simultaneous Scheduling, Binding and Routing for Coarse-Grain Reconfigurable Architectures.	Electronic Notes in Discrete Mathematics	2006	DBLP DOI BibTeX RDF
1	Frederic Desprez, Antoine Vernois	Simultaneous Scheduling of Replication and Computation for Data-Intensive Applications on the Grid.	J. Grid Comput.	2006	DBLP DOI BibTeX RDF	bioinformatics applications, scheduling, Grid computing, data management
1	Janina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang Rosenstiel	Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
1	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.	ASP-DAC	2006	DBLP DOI BibTeX RDF	granularity selection, linear placement, scheduling, data-parallelism, partial dynamic reconfiguration
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Mineo Kaneko	Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee	Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
1	Frederic Desprez, Antoine Vernois, Christophe Blanchet	Simultaneous Scheduling of Replication and Computation for Bioinformatic Applications on the Grid.	ISBMDA	2005	DBLP DOI BibTeX RDF
1	Ling Wang, Yingtao Jiang, Yu Zhang, Ru Chen	A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Loris Marchal, Yang Yang, Henri Casanova, Yves Robert	A Realistic Network/Application Model for Scheduling Divisible Loads on Large-Scale Platforms.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Madhubanti Mukherjee, Ranga Vemuri	Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.	ICCD	2004	DBLP DOI BibTeX RDF
1	Dongku Kang, Mark C. Johnson, Kaushik Roy	Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.	ISQED	2004	DBLP DOI BibTeX RDF
1	Philip Holman, James H. Anderson	Implementing Pfairness on a Symmetric Multiprocessor.	IEEE Real-Time and Embedded Technology and Applications Symposium	2004	DBLP DOI BibTeX RDF
1	Saravana S. Sankar, R. Rajkumar, Sivalinga Govindarajan Ponnambalam, M. Gurumarimuthu	Integrated scheduling of material handling and manufacturing activities in flexible manufacturing system.	SMC	2004	DBLP DOI BibTeX RDF
1	Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang	Architecture and synthesis for on-chip multicycle communication.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami	Semiconcurrent Error Detection in Data Paths.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Semiconcurrent error detection, checking periodicity, resource minimization, fault tolerance, high-level synthesis, data flow graph, self-checking circuits
1	Sophie Bonneau, Abdelkader Hameurlain	Hybrid Simultaneous Scheduling and Mapping in SQL Multi-query Parallelization.	DEXA	1999	DBLP DOI BibTeX RDF
1	Fabrício Alves Barbosa da Silva, Isaac D. Scherson	Improvements in Parallel Job Scheduling Using Gang Service.	ISPAN	1999	DBLP DOI BibTeX RDF	parallel computing, gang scheduling, parallel job scheduling
1	Anna Antola, Vincenzo Piuri, Mariagiovanna Sami	A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths.	DATE	1998	DBLP DOI BibTeX RDF	Semi-concurrent error detection, Fault tolerance, High-level synthesis, Data Flow Graphs, Self-checking circuits
1	Gündüz Ulusoy, Funda Sivrikaya-Serifoglu, Ümit Bilge	A genetic algorithm approach to the simultaneous scheduling of machines and automated guided vehicles.	Computers & OR	1997	DBLP DOI BibTeX RDF
1	Aurobindo Dasgupta, Ramesh Karri	Simultaneous scheduling and binding for power minimization during microarchitecture synthesis.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Birger Landwehr, Peter Marwedel, Rainer Dömer	OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.	EURO-DAC	1994	DBLP DOI BibTeX RDF
1	Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji	An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.	ICCD	1994	DBLP BibTeX RDF
1	Qi Ning	Register allocation for optimal loop scheduling.	CASCON	1993	DBLP DOI BibTeX RDF
1	Qi Ning, Guang R. Gao	A Novel Framework of Register Allocation for Software Pipelining.	POPL	1993	DBLP DOI BibTeX RDF
1	Catherine H. Gebotys	Throughput optimized architectural synthesis.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
1	Catherine H. Gebotys, Mohamed I. Elmasry	Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.	DAC	1991	DBLP DOI BibTeX RDF