Search results for "single event upsets (SEUs)"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff	Soft Delay Error Effects in CMOS Combinational Circuits.	VTS	2004	DBLP DOI BibTeX RDF	Soft delay, single event upsets (SEUs), soft error rate (SER), soft errors
1	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
1	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.	ARC	2009	DBLP DOI BibTeX RDF	FPGA, Space, Reconfigurable System, Single Event Upsets, Avionics
1	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
1	Rajesh Garg, Peng Li, Sunil P. Khatri	Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).	ISCAS	2008	DBLP DOI BibTeX RDF
1	Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano	Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	single event upsets (SEUs), multiple bit upsets (MBUs), fault tolerance, redundancy, soft errors, interleaving
1	Rajesh Garg, Charu Nagpal, Sunil P. Khatri	A fast, analytical estimator for the SEU-induced pulse width in combinational designs.	DAC	2008	DBLP DOI BibTeX RDF	single event upset (SEU), model, analysis
1	Juan Antonio Maestro, Pedro Reviriego	Study of the effects of MBUs on the reliability of a 150 nm SRAM device.	DAC	2008	DBLP DOI BibTeX RDF	multiple bit upsets (MBUs), reliability, memory, radiation
1	Yantu Mo, Suge Yue	An Efficient Design of Single Event Transients Tolerance for Logic Circuits.	DELTA	2008	DBLP DOI BibTeX RDF	integrated circuit, Single Event Upset, Single Event Transients
1	Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sarrafzadeh	Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems.	ISQED	2008	DBLP DOI BibTeX RDF
1	Makoto Sugihara	SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems.	ISQED	2008	DBLP DOI BibTeX RDF	Heterogeneous Multiprocessor Systems, Reliability, Task Scheduling, Soft Error, Single Event Upset
1	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Chong Zhao, Yi Zhao, Sujit Dey	Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro	Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	reliability, fault tolerant systems, SEU, SRAM-based FPGA
1	Navid Azizi, Farid N. Najm	A family of cells to reduce the soft-error-rate in ternary-CAM.	DAC	2006	DBLP DOI BibTeX RDF	soft-error rate, content-addressable memory
1	Mihir R. Choudhury, Quming Zhou, Kartik Mohanram	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis	Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.	SBCCI	2006	DBLP DOI BibTeX RDF	fault-tolerant microprocessor, soft errors, single event upsets, single event transients
1	Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota	Evaluation of SEU and crosstalk effects in network-on-chip switches.	SBCCI	2006	DBLP DOI BibTeX RDF	network-on-chip, crosstalk, single-event upset
1	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
1	Sajid Baloch, Tughrul Arslan, Adrian Stoica	An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
1	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis	Design of a Robust 8-Bit Microprocessor to Soft Errors.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Melanie Berg	Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Maico Cassel, Fernanda Lima Kastensmidt	Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Arthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt	Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Bernhard Fechner	Analysis of checksum-based execution schemes for pipelined processors.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Chong Zhao, Sujit Dey	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).	ISQED	2006	DBLP DOI BibTeX RDF
1	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Quming Zhou, Mihir R. Choudhury, Kartik Mohanram	Design Optimization for Robustness to Single Event Upsets.	VTS	2006	DBLP DOI BibTeX RDF
1	Quming Zhou, Kartik Mohanram	Gate sizing to radiation harden combinational logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Luca Sterpone, Massimo Violante	A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	transient fault injection, FPGA, reliability, place and route
1	Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
1	Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA
1	Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick	An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.	DATE	2005	DBLP DOI BibTeX RDF
1	Haruhiko Kaneko	Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment.	DFT	2005	DBLP DOI BibTeX RDF
1	Jeetendra Kumar, Mehdi Baradaran Tahoori	A Low Power Soft Error Suppression Technique for Dynamic Logic.	DFT	2005	DBLP DOI BibTeX RDF
1	Luca Sterpone, Massimo Violante	A design flow for protecting FPGA-based systems against single event upsets.	DFT	2005	DBLP DOI BibTeX RDF
1	Jonny Vinter, Olof Hannius, Torbjörn Norlander, Peter Folkesson, Johan Karlsson	Experimental Dependability Evaluation of a Fail-Bounded Jet Engine Control System for Unmanned Aerial Vehicles.	DSN	2005	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
1	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft Error Mitigation for SRAM-Based FPGAs.	VTS	2005	DBLP DOI BibTeX RDF
1	Kartik Mohanram	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.	VTS	2005	DBLP DOI BibTeX RDF
1	David de Andrés, José Albaladejo, Lenin Lemus, Pedro J. Gil	Fast Run-Time Reconfiguration for SEU Injection.	EDCC	2005	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.	PRDC	2004	DBLP DOI BibTeX RDF
1	Tanay Karnik, Peter Hazucha, Jagdish Patel	Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.	IEEE Trans. Dependable Sec. Comput.	2004	DBLP DOI BibTeX RDF	reliability, High performance, soft error, error tolerance, single event upset
1	André K. Nieuwland, Richard P. Kleihorst	IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR
1	Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham	The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets.	FCCM	2003	DBLP DOI BibTeX RDF
1	Daniel Mossé, Rami G. Melhem, Sunondo Ghosh	A Nonpreemptive Real-Time Scheduler with Recovery from Transient Faults and Its Implementation.	IEEE Trans. Software Eng.	2003	DBLP DOI BibTeX RDF	scheduling, Fault tolerance, real-time, operating system, transient faults
1	Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus	On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	cross-parity check, on-line BIST, multiple soft-error detection, self-repair
1	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF