Search results for "single instruction multiple data"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2		Single Instruction Multiple Data (SIMD) Parallelism.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	AnySP: anytime anywhere anyway signal processing.	ISCA	2009	DBLP DOI BibTeX RDF	fully programmable architecture, high-end signal processing, single-instruction multiple-data parallelism, software defined radio, low-power architecture, simd
2	Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard Seymour, Weiqiang Wang, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta	A Multilevel Parallelization Framework for High-Order Stencil Computations.	Euro-Par	2009	DBLP DOI BibTeX RDF	single instruction multiple data parallelism, spatial decomposition, message passing, multithreading, Stencil computation
2	Wonchul Lee, Hyojin Choi, Wonyong Sung	Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data)
2		SIMD (Single Instruction Multiple Data) Processing.	Encyclopedia of Multimedia	2006	DBLP DOI BibTeX RDF
2	Sanjay Ranka, Sartaj Sahni	Clustering on a Hypercube Multicomputer.	IEEE Trans. Parallel Distrib. Syst.	1991	DBLP DOI BibTeX RDF	square error, clustering problem, NMK processors, multiple-data, parallel algorithms, computational complexity, hypercube networks, single-instruction multiple-data, SIMD, MIMD, hypercube multicomputer, multiple-instruction
2	Edward W. Krauser, Aditya P. Mathur, Vernon Rego	High Performance Software Testing on SIMD Machines.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	mutant unification, program mutation, single instruction multiple data stream, software testing, software reliability, software reliability, program testing, parallel machines, parallel machines, software systems, SIMD machines
1	Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani	A high-performance sorting algorithm for multicore single-instruction multiple-data processors.	Softw., Pract. Exper.	2012	DBLP DOI BibTeX RDF
1		SIMD (Single Instruction, Multiple Data) Machines.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Kudlur, Rodric M. Rabbah, Trevor N. Mudge, Scott A. Mahlke	MacroSS: macro-SIMDization of streaming applications.	ASPLOS	2010	DBLP DOI BibTeX RDF	optimization, compiler, streaming, SIMD architecture
1	Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrigo Dominguez, David R. Kaeli	Data transformations enabling loop vectorization on multithreaded data parallel architectures.	PPOPP	2010	DBLP DOI BibTeX RDF	loop vectorization, gpgpu, data transformation
1	Kanupriya Gulati, Sunil P. Khatri	Accelerating statistical static timing analysis using graphics processing units.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, Qiong Luo	Frequent itemset mining on graphics processors.	DaMoN	2009	DBLP DOI BibTeX RDF
1	Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala	A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	performance, design
1	David Strippgen, Kai Nagel	Using common graphics hardware for multi-agent traffic simulation with CUDA.	SimuTools	2009	DBLP DOI BibTeX RDF
1	Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt	Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware.	TACO	2009	DBLP DOI BibTeX RDF	fine-grained multithreading, GPU, SIMD, control flow
1	James R. Green, Hanan Mahmoud, Michel Dumontier	Modeling tryptic digestion on the Cell BE processor.	CCECE	2009	DBLP DOI BibTeX RDF
1	Liu Peng, Richard Seymour, Ken-ichi Nomura, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta, Alexander Loddoch, Michael Netzband, William R. Volz, Chap C. Wong	High-order stencil computations on multicore clusters.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Hoseok Chang, Wonyong Sung	Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Pascal Junod, Marco Macchetti	Revisiting the IDEA Philosophy.	FSE	2009	DBLP DOI BibTeX RDF	IDEA block cipher, WIDEA compression function, Intel Core2 CPU, wordslice implementation
1	Peter Westermann, Hartmut Schröder	Modeling Scalable SIMD DSPs in LISA.	SAMOS	2009	DBLP DOI BibTeX RDF	SIMD DSPs, Scalable Processor Models, LISA
1	Hoseok Chang, Junho Cho, Wonyong Sung	Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Multi-bank memory, Vectorizing compiler, Data allocation, On-chip memory, SIMD processor
1	David Novo, Thomas Schuster, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor	Energy-performance Exploration of a CGA-based SDR Processor.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Coarse grain arrays, SDR terminals, Low power, Architecture exploration
1	Anas N. Al-Rabadi	Reversible Systolic Arrays: M-Ary Bijective Single-Instruction Multiple-Data (SIMD) Architectures and their Quantum Circuits.	Journal of Circuits, Systems, and Computers	2008	DBLP DOI BibTeX RDF
1	Robert D. Cameron, Kenneth S. Herdy, Dan Lin	High performance XML parsing using parallel bit stream technology.	CASCON	2008	DBLP DOI BibTeX RDF
1	Hoseok Chang, Wonyong Sung	Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware.	CASES	2008	DBLP DOI BibTeX RDF	irregular access, non-aligned access, packing buffer, split line buffer, compiler, SIMD, vectorization
1	Kanupriya Gulati, Sunil P. Khatri	Towards acceleration of fault simulation using graphics processing units.	DAC	2008	DBLP DOI BibTeX RDF	graphics processing units, fault simulation
1	Ali El-Moursy, Ahmed El-Mahdy, Hisham El-Shishiny	An efficient in-place 3D transpose for multicore processors with software managed memory hierarchy.	IFMT	2008	DBLP DOI BibTeX RDF	3D transpose, vector programming, parallel programming, SIMD, multi-core systems
1	David Novo, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor	Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.	DATE	2008	DBLP DOI BibTeX RDF
1	Igor Majdandzic, Christian Trefftz, Gregory Wolffe	Computation of Voronoi diagrams using a graphics processing unit.	EIT	2008	DBLP DOI BibTeX RDF
1	Mark Woh, Yuan Lin, Sangwon Seo, Trevor N. Mudge, Scott A. Mahlke	Analyzing the scalability of SIMD for the next generation software defined radio.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Bo Li, Hai Jin, Zhiyuan Shao	Two-Level Parallel Implementation of FDTD Algorithm on CBE.	ICNSC	2008	DBLP DOI BibTeX RDF
1	Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal	DC-SIMD : Dynamic communication for SIMD processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus	Wait-free Programming for General Purpose Computations on Graphics Processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Chen Wu, Hamid K. Aghajan, Richard P. Kleihorst	Real-Time Human Posture Reconstruction in Wireless Smart Camera Networks.	IPSN	2008	DBLP DOI BibTeX RDF	embedded vision systems, human posture estimation, smart cameras
1	Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner	From SODA to scotch: The evolution of a wireless baseband processor.	MICRO	2008	DBLP DOI BibTeX RDF
1	Hyungwook Park, Paul A. Fishwick	A fast hybrid time-synchronous/event approach to parallel discrete event simulation of queuing networks.	Winter Simulation Conference	2008	DBLP DOI BibTeX RDF
1	Patrick Longa, Ali Miri	Fast and Flexible Elliptic Curve Point Arithmetic over Prime Fields.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Parallel, Public key cryptosystems, High-Speed Arithmetic
1	Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal, Bart Mesman	Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration.	ACIVS	2008	DBLP DOI BibTeX RDF
1	Branimir Lambov	Interval Arithmetic Using SSE-2.	Reliable Implementation of Real Number Algorithms	2008	DBLP DOI BibTeX RDF
1	Wesley Alvaro, Jakub Kurzak, Jack Dongarra	Fast and Small Short Vector SIMD Matrix Multiplication Kernels for the Synergistic Processing Element of the CELL Processor.	ICCS	2008	DBLP DOI BibTeX RDF
1	Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho	On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine.	VECPAR	2008	DBLP DOI BibTeX RDF	Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements
1	Aart J. C. Bik, David L. Kreitzer, Xinmin Tian	A Case Study on Compiler Optimizations for the Intel® CoreTM 2 Duo Processor.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Optimization, Parallelization, Compilers, Code generation, Vectorization
1	Richard Hughey, Andrea Di Blas	Finding the Next Computational Model: Experience with the UCSC Kestrel.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers
1	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
1	Luca Sterpone, Massimo Violante	A new hardware architecture for performing the gridding of DNA microarray images.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	image data-processing, FPGA, edge detection, DNA microarray
1	Timothy Furtak, José Nelson Amaral, Robert Niewiadomski	Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms.	SPAA	2007	DBLP DOI BibTeX RDF	sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort
1	Libo Huang, Li Shen, Kui Dai, Zhiying Wang	A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Richard P. Kleihorst, Anteneh A. Abbo, Ben Schueler, Alexander Danilin	Camera mote with a high-performance parallel processor for real-time frame-based video processing.	AVSS	2007	DBLP DOI BibTeX RDF
1	Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vetter	Balancing productivity and performance on the cell broadband engine.	CLUSTER	2007	DBLP DOI BibTeX RDF
1	Jaewook Shin	Introducing Control Flow into Vectorized Code.	PACT	2007	DBLP DOI BibTeX RDF
1	Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto	Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Xiaofang Wang, Sotirios G. Ziavras	Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors.	ISQED	2007	DBLP DOI BibTeX RDF
1	Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt	Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow.	MICRO	2007	DBLP DOI BibTeX RDF
1	Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen	Hardware Support for Arithmetic Units of Processor with Multimedia Extension.	MUE	2007	DBLP DOI BibTeX RDF
1	Robert A. Tefft, Roger Y. Lee	Reduction of Complexity and Automation of Parallel Execution through Loop Level Parallelism.	QSIC	2007	DBLP DOI BibTeX RDF
1	C. J. Duanmu, M. Omair Ahmad, M. N. S. Swamy	Fast Block Motion Estimation With 8-Bit Partial Sums Using SIMD Architectures.	IEEE Trans. Circuits Syst. Video Techn.	2007	DBLP DOI BibTeX RDF
1	I. K. Hong, S. T. Chung, H. K. Kim, Y. B. Kim, Y. D. Son, Z. H. Cho	Ultra Fast Symmetry and SIMD-Based Projection-Backprojection (SSP) Algorithm for 3-D PET Image Reconstruction.	IEEE Trans. Med. Imaging	2007	DBLP DOI BibTeX RDF
1	Myoung-Cheol Shin, In-Cheol Park	SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Hyun-Ho Kang, Jae-Myung Kim, Gap-Joo Na, Sang-Won Lee	Implementation of Bitmap Based Incognito and Performance Evaluation.	DASFAA	2007	DBLP DOI BibTeX RDF
1	Yi Qian, Ang Li, Qin Wang	Design and Implementation of a General Purpose Neural Network Processor.	ISNN	2007	DBLP DOI BibTeX RDF
1	Yogesh Gupta, Sriram Sethuraman	A Low Complexity Block-Based Video De-interlacing Algorithm for SIMD Processors.	PCM	2007	DBLP DOI BibTeX RDF	Interlaced, de-interlacing, pre-/post-processing, motion detection, spatio-temporal, progressive, SIMD processors, block-based
1	Sándor M. Szilágyi, László Szilágyi, Zoltán Benyó	Spatial Visualization of the Heart in Case of Ectopic Beats and Fibrillation.	PSIVT	2007	DBLP DOI BibTeX RDF	heart wall movement analysis, parallel processing, spatial visualization
1	Muhammad Omer Cheema, Omar Hammami	Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization.	ASP-DAC	2006	DBLP DOI BibTeX RDF	AltiVec architecture, SIMD synthesis, vectorization, HW/SW codesign
1	Dorit Nuzman, Ira Rosen, Ayal Zaks	Auto-vectorization of interleaved data for SIMD.	PLDI	2006	DBLP DOI BibTeX RDF	SIMD, vectorization, data reuse, subword parallelism, Viterbi
1	Julien Mairal, Renaud Keriven, Alexandre Chariot	Fast and Efficient Dense Variational Stereo on GPU.	3DPVT	2006	DBLP DOI BibTeX RDF
1	C. J. Duanmu	A Fast Hexagon-Based Search Algorithm on SIMD Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
1	C. J. Duanmu	Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance Values.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Luo Jianwen, Jong Ching Chuen	Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Richard Hughey, Andrea Di Blas	The UCSC Kestrel Application-Unspecific Processor.	ASAP	2006	DBLP DOI BibTeX RDF
1	Jianhui Li, Qi Zhang, Shu Xu, Bo Huang 0002	Optimizing Dynamic Binary Translation for SIMD Instructions.	CGO	2006	DBLP DOI BibTeX RDF
1	Dorit Nuzman, Richard Henderson	Multi-platform Auto-vectorization.	CGO	2006	DBLP DOI BibTeX RDF
1	Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun	VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.	IIH-MSP	2006	DBLP DOI BibTeX RDF
1	Yinbo Li, Christopher D. Garson, Frederick H. Epstein, Brent A. French, John A. Hossack	High resolution 2D quantification of myocardial motion abnormalities in mice using high resolution ultrasound with MRI validation.	ISBI	2006	DBLP DOI BibTeX RDF
1	Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner	SODA: A Low-power Architecture For Software Radio.	ISCA	2006	DBLP DOI BibTeX RDF
1	S. Balam, Dan Schonfeld	Associative processors for video coding applications.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
1	Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu	Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture.	LCPC	2006	DBLP DOI BibTeX RDF
1	Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis	Avoiding Conversion and Rearrangement Overhead in SIMD Architectures.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	Embedded media processors, multimedia kernels, register file, subword parallelism
1	Nigel C. Paver, Moinul H. Khan, B. C. Aldrich	Optimizing mobile multimedia using SIMD techniques.	Multimedia Tools Appl.	2006	DBLP DOI BibTeX RDF	Multimedia, Mobile, Architecture, Programming, SIMD
1	Michael Hosemann, Gerhard Fettweis	On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF
1	V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj	Performance Analysis of Embedded Media Applications in Newer ARM Architectures.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD)
1	William H. Robinson, D. Scott Wills	Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	focal plane processing, digital pixel, area-time efficiency, energy efficiency, single-instruction multiple-data (SIMD), area efficiency
1	Luigi di Stefano, Stefano Mattoccia, Federico Tombari	Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions.	CAMP	2005	DBLP DOI BibTeX RDF
1	Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind	Optimizing Compiler for the CELL Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster	Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Wen-Kai Huang, I-Ting Lin, Shi-Wei Chen, Ing-Jer Huang	A cost-effective media processor for embedded applications [audio decoder example].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Implementing and Evaluating Color-Aware Instruction Set for Low-Memory, Embedded Video Processing in Data Parallel Architectures.	EUC	2005	DBLP DOI BibTeX RDF
1	Dongsun Kim, Hyunsik Kim, Hong-Sik Kim, Gunhee Han, Duckjin Chung	A SIMD Neural Network Processor for Image Processing.	ISNN	2005	DBLP DOI BibTeX RDF
1	Nigel C. Paver, Moinul H. Khan, B. C. Aldrich, C. D. Emmons	Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	architecture, SIMD, SOC, multi-media, wireless video
1	Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers	Compiler based exploration of DSP energy savings by SIMD operations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Raymond Hoare, Shen Chih Tung, Katrina Werger	An 88-Way Multiprocessor within an FPGA with Customizable Instructions.	IPDPS	2004	DBLP DOI BibTeX RDF	FPGA, Architecture, Parallelism, DSP, SIMD
1	Sandeep Koranne	A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform.	ISQED	2004	DBLP DOI BibTeX RDF
1	Tomasz Madajczak	An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Jong Won Park	Multiaccess Memory System for Attached SIMD Computer.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	prime memory system, multiaccess memory system, conflict-free memory system, routing circuit, SIMD computer, address calculation
1	Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo	Variable precision arithmetic circuits for FPGA-based multimedia processors.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Yu-Fai Fung, Muhammet Fikret Ercan, Wai-leung Cheung, Gujit Singh	Avenues for High Performance Computation on a PC.	ICCSA	2004	DBLP DOI BibTeX RDF
1	Hiroyuki Takizawa, Hiroaki Kobayashi	Multi-grain Parallel Processing of Data-Clustering on Programmable Graphics Hardware.	ISPA	2004	DBLP DOI BibTeX RDF
1	Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat	Power Consumption of Performance-Scaled SIMD Processors.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Michael Hosemann, Gerhard Fettweis	On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering.	SAMOS	2004	DBLP DOI BibTeX RDF