Search results for "single-thread performance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Md Kamruzzaman, Steven Swanson, Dean M. Tullsen	Software data spreading: leveraging distributed caches to improve single thread performance.	PLDI	2010	DBLP DOI BibTeX RDF	single-thread performance, compilers, chip multiprocessors
3	Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González	Boosting single-thread performance in multi-core systems through fine-grain multi-threading.	ISCA	2009	DBLP DOI BibTeX RDF	core-fusion, single-thread performance, multicore, automatic parallelization, thread-level parallelism, speculative multithreading
2	Peng Zhou, Soner Önder	Improving single-thread performance with fine-grain state maintenance.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	processor state, runahead, simultaneous multi-threading, checkpoint, recovery
2	Brian Greskamp, Josep Torrellas	Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking.	PACT	2007	DBLP DOI BibTeX RDF
2	Gautham K. Dorai, Donald Yeung	Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	Geoffrey Ndu, Jim D. Garside	Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration.	ARC	2012	DBLP DOI BibTeX RDF
1	Rania H. Mameesh, Manoj Franklin	Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance.	PACT	2010	DBLP DOI BibTeX RDF
1	Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas	LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores.	HPCA	2010	DBLP DOI BibTeX RDF
1	Dong Hyuk Woo, Hsien-Hsin S. Lee	COMPASS: a programmable data prefetcher using idle GPU shaders.	ASPLOS	2010	DBLP DOI BibTeX RDF	compute shader, GPU, prefetch
1	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
1	John A. Stratton, Vinod Grover, Jaydeep Marathe, Bastiaan Aarts, Mike Murphy, Ziang Hu, Wen-mei W. Hwu	Efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs.	CGO	2010	DBLP DOI BibTeX RDF	multicore, CUDA, CPU, SPMD
1	William J. Dally	Throughput computing.	ICS	2010	DBLP DOI BibTeX RDF	parallelism and locality, throughput processors, GPU, power efficiency
1	Yasuko Watanabe, John D. Davis, David A. Wood	WiDGET: Wisconsin decoupled grid execution tiles.	ISCA	2010	DBLP DOI BibTeX RDF	instruction steering, power proportional computing, performance, hardware, power efficiency
1	Takuya Nakaike, Maged M. Michael	Lock elision for read-only critical sections in Java.	PLDI	2010	DBLP DOI BibTeX RDF	lock elision, java, optimization, synchronization, monitor, lock, just-in-time compiler
1	Cheng Wang, Youfeng Wu, Edson Borin, Shiliang Hu, Wei Liu, Dave Sager, Tin-fook Ngai, Jesse Fang	Dynamic parallelization of single-threaded binary programs using speculative slicing.	ICS	2009	DBLP DOI BibTeX RDF	backward slicing, binary optimization, single-thread performance, parallelization, speculations
1	Ronny Ronen	Larrabee: a many-core Intel architecture for visual computing.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, parrallel processing, processor arechitecture, software rendering
1	Ryan Johnson, Ippokratis Pandis, Nikos Hardavellas, Anastasia Ailamaki, Babak Falsafi	Shore-MT: a scalable storage manager for the multicore era.	EDBT	2009	DBLP DOI BibTeX RDF
1	Don G. Grice	The roadrunner project and the importance of energy efficiency on the road to exascale computing.	ICS	2009	DBLP DOI BibTeX RDF	exaflop, exascale computing, heterogeneous multicore architectures, petaflop, cell broadband engine
1	Andrew D. Hilton, Santosh Nagarakatte, Amir Roth	iCFP: Tolerating all-level cache misses in in-order processors.	HPCA	2009	DBLP DOI BibTeX RDF
1	Hashem Hashemi Najaf-abadi, Eric Rotenberg	Architectural Contesting.	HPCA	2009	DBLP DOI BibTeX RDF
1	R. K. Archibald, Katherine J. Evans, J. B. Drake, James B. White III	Time Acceleration Methods for Advection on the Cubed Sphere.	ICCS	2009	DBLP DOI BibTeX RDF
1	Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge	Reconfigurable Multicore Server Processors for Low Power Operation.	SAMOS	2009	DBLP DOI BibTeX RDF	Server Architectures, Low Power, Reconfigurable
1	Yaron Weinsberg, Danny Dolev, Tal Anker, Muli Ben-Yehuda, Pete Wyckoff	Tapping into the fountain of CPUs: on operating system support for programmable devices.	ASPLOS	2008	DBLP DOI BibTeX RDF	operating systems, programming model, offloading
1	David Tarjan, Michael Boyer, Kevin Skadron	Federation: repurposing scalar cores for out-of-order instruction issue.	DAC	2008	DBLP DOI BibTeX RDF	CMP, multicore, federation, out-of-order
1	Andrey Brito, Christof Fetzer, Heiko Sturzrehm, Pascal Felber	Speculative out-of-order event processing with software transaction memory.	DEBS	2008	DBLP DOI BibTeX RDF	software transactional memory, event stream processing
1	Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh	On the potential of latency tolerant execution in speculative multithreading.	IFMT	2008	DBLP DOI BibTeX RDF	latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors
1	Andrey Brito	Optimistic parallelization support for event stream processing systems.	Middleware (Doctoral Symposium)	2008	DBLP DOI BibTeX RDF	software transactional memory, optimistic parallelization, event stream processing
1	Evgueni Brevnov, Yuri Dolgov, Boris Kuznetsov, Dmitry Yershov, Vyacheslav Shakin, Dong-yuan Chen, Vijay Menon, Suresh Srinivas	Practical experiences with Java software transactional memory.	PPOPP	2008	DBLP DOI BibTeX RDF	atomic constructs, managed runtimes, stm performance analysis, stm workloads, software transactional memory, runtime environment
1	Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song	A simple latency tolerant processor.	ICCD	2008	DBLP DOI BibTeX RDF
1	Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles	Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation.	IEEE Micro	2008	DBLP DOI BibTeX RDF	Java, optimization, architecture, compiler, checkpoint, atomicity, speculation, isolation, compiler-architecture interactions
1	Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles	Hardware atomicity for reliable software speculation.	ISCA	2007	DBLP DOI BibTeX RDF	Java, optimization, checkpoint, atomicity, speculation, isolation
1	Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha	Transactional programming in a multi-core environment.	PPOPP	2007	DBLP DOI BibTeX RDF	parallel programming, transactional memory, atomicity, hardware architecture
1	Ron Gabor, Shlomo Weiss, Avi Mendelson	Fairness enforcement in switch on event multithreading.	TACO	2007	DBLP DOI BibTeX RDF	SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading
1	Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos	Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy	Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.	ASPLOS	2006	DBLP DOI BibTeX RDF	redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
1	Marc Tremblay	A modern high-performance processor pipeline.	ICS	2006	DBLP DOI BibTeX RDF
1	Ron Gabor, Shlomo Weiss, Avi Mendelson	Fairness and Throughput in Switch on Event Multithreading.	MICRO	2006	DBLP DOI BibTeX RDF
1	Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson	Architectural Support for Software Transactional Memory.	MICRO	2006	DBLP DOI BibTeX RDF
1	Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew	Supporting Speculative Multithreading on Simultaneous Multithreaded Processors.	HiPC	2006	DBLP DOI BibTeX RDF
1	Charlie Johnson, Jeff Welser	Future processors: flexible and modular.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	multiprocessor, SoC, accelerators
1	Huiyang Zhou	Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt	An Introduction to the Plasma Language.	MTV	2005	DBLP DOI BibTeX RDF
1	Shailender Chaudhry, Paul Caprioli, Sherman Yip, Marc Tremblay	High-Performance Throughput Computing.	IEEE Micro	2005	DBLP DOI BibTeX RDF	hardware scout, CMP, multithreading, multicore, microprocessor, CMT
1	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Throughput.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade off, processor architecture, SMT
1	Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton	Continual flow pipelines.	ASPLOS	2004	DBLP DOI BibTeX RDF	CFP, non-blocking, latency tolerance, instruction window
1	Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.	ISCA	2004	DBLP DOI BibTeX RDF
1	Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton	Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Gautham Thambidorai, Donald Yeung, Seungryul Choi	Optimizing SMT Processors for High Single-Thread Performance.	J. Instruction-Level Parallelism	2003	DBLP BibTeX RDF
1	Theo Ungerer, Borut Robic, Jurij Silc	A survey of processors with explicit multithreading.	ACM Comput. Surv.	2003	DBLP DOI BibTeX RDF	interleaved multithreading, simultaneous multithreading, Blocked multithreading
1	Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque	Improving Single-Thread Fetch Performance on a Multithreaded Processor.	DSD	2001	DBLP DOI BibTeX RDF
1	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	Todd C. Mowry, Sherwyn R. Ramkissoon	Software-Controlled Multithreading Using Informing Memory Operations.	HPCA	2000	DBLP DOI BibTeX RDF	shared-memory multiprocessing, Multithreading, cache performance
1	Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen	A Realistic Study on Multithreaded Superscalar Processor Design.	Euro-Par	1997	DBLP DOI BibTeX RDF