Search results for "soft error"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	Accelerating Soft Error Rate Testing Through Pattern Selection.	IOLTS	2007	DBLP DOI BibTeX RDF	soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error
4	Alodeep Sanyal, Sandip Kundu	On Derating Soft Error Probability Based on Strength Filtering.	IOLTS	2007	DBLP DOI BibTeX RDF	soft error rate, logic switching threshold voltage, Soft error, single event upset, single event transient
3	Syed Zafar Shazli, Mehdi Baradaran Tahoori	Soft error rate computation in early design stages using boolean satisfiability.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	soft error, hardware description language, reliability modeling
3	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
3	Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev	Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.	ISQED	2008	DBLP DOI BibTeX RDF	critical charge, process variation, Soft error, SRAM
3	Kaushal R. Gandhi, Nihar R. Mahapatra	Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass.	VLSI Design	2008	DBLP DOI BibTeX RDF	operand encoding, opera- tion bypass, low-power design, soft error
3	Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan	A soft error robust and power aware memory design.	SBCCI	2007	DBLP DOI BibTeX RDF	robustness, memory, soft error, power aware
3	Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto	A Simulation-Based Soft Error Estimation Methodology for Computer Systems.	ISQED	2006	DBLP DOI BibTeX RDF	Reliability, Estimation, Soft Error, Computer Systems, Instruction-Set Simulation
3	Navid Azizi, Farid N. Najm	A family of cells to reduce the soft-error-rate in ternary-CAM.	DAC	2006	DBLP DOI BibTeX RDF	soft-error rate, content-addressable memory
3	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA
3	Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang	Logic soft errors in sub-65nm technologies design and CAD challenges.	DAC	2005	DBLP DOI BibTeX RDF	architectural vulnerability factor, built-in soft error resilience, derating, error blocking, error detection, recovery, soft error
2	Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee	UnSync: A Soft Error Resilient Redundant Multicore Architecture.	ICPP	2011	DBLP DOI BibTeX RDF	core-level redundancy, redundant architecture, hardware detection, low power, soft error, error resilient, multi-core architecture
2	Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke	Shoestring: probabilistic soft error reliability on the cheap.	ASPLOS	2010	DBLP DOI BibTeX RDF	error detection, fault injection, compiler analysis
2	Xin He, Afshin Abdollahi	Cost aware fault tolerant logic synthesis in presence of soft errors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	soft error rate, reliability, linear programming
2	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	An Improved Soft-Error Rate Measurement Technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Koustav Bhattacharya, Nagarajan Ranganathan	A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations.	ISQED	2009	DBLP DOI BibTeX RDF
2	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
2	Jongeun Lee, Aviral Shrivastava	Compiler-managed register file protection for energy-efficient soft error reduction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Fan Wang, Vishwani D. Agrawal	Soft Error Rates with Inertial and Logical Masking.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
2	Sobeeh Almukhaizim, Yiorgos Makris	Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires.	IEEE Transactions on Reliability	2008	DBLP DOI BibTeX RDF
2	Natasa Miskov-Zivanov, Diana Marculescu	Modeling and Optimization for Soft-Error Reliability of Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	Self-Adaptive Data Caches for Soft-Error Reliability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Qian Ding, Yu Wang 0002, Hui Wang 0004, Rong Luo, Huazhong Yang	Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.	ISQED	2008	DBLP DOI BibTeX RDF
2	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
2	Muhammad Sheikh Sadi, D. G. Myers, Cesar Ortega Sanchez	A Design Approach for Soft Error Protection in Real-Time Embedded Systems.	Australian Software Engineering Conference	2008	DBLP DOI BibTeX RDF	Real-Time Embedded Systems and Metrics, Soft Error
2	Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.	HASE	2008	DBLP DOI BibTeX RDF
2	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
2	Wangyuan Zhang, Tao Li	Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.	MICRO	2008	DBLP DOI BibTeX RDF
2	Jong Kang Park, Hyun Suk Choi, Jong Tae Kim	A soft error analysis tool for high-speed digital designs.	ICUIMC	2008	DBLP DOI BibTeX RDF
2	Wangyuan Zhang, Tao Li	Managing multi-core soft-error reliability through utility-driven cross domain optimization.	ASAP	2008	DBLP DOI BibTeX RDF
2	Kai-Chiang Wu, Diana Marculescu	Soft error rate reduction using redundancy addition and removal.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Greg Bronevetsky, Bronis R. de Supinski	Soft error vulnerability of iterative linear algebra methods.	ICS	2008	DBLP DOI BibTeX RDF	fault tolerance, parallel, iterative methods, linear algebra, soft errors
2	Vikas Chandra, Robert C. Aitken	Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.	DFT	2008	DBLP DOI BibTeX RDF
2	Shubu Mukherjee	Architectural Vulnerability Factor (or, does a soft error matter?).	DFT	2008	DBLP DOI BibTeX RDF
2	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Soft Error Hardened FF Capable of Detecting Wide Error Pulse.	DFT	2008	DBLP DOI BibTeX RDF
2	Kaushal R. Gandhi, Nihar R. Mahapatra	Partitioned reuse cache for energy-efficient soft-error protection of functional units.	SoCC	2008	DBLP DOI BibTeX RDF
2	Srivathsan Krishnamohan, Nihar R. Mahapatra	Slack redistribution in pipelined circuits for enhanced soft-error rate reduction.	SoCC	2008	DBLP DOI BibTeX RDF
2	Kai-Chiang Wu, Diana Marculescu	Power-aware soft error hardening via selective voltage scaling.	ICCD	2008	DBLP DOI BibTeX RDF
2	Weiguang Sheng, Liyi Xiao, Zhigang Mao	An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.	DELTA	2008	DBLP DOI BibTeX RDF	simulated fault injection, reliability, VLSI, soft error, stratified sampling
2	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
2	Jun Won Choi, Byonghyo Shim, Andrew C. Singer, Nam Ik Cho	Low-Power Filtering Via Minimum Power Soft Error Cancellation.	IEEE Transactions on Signal Processing	2007	DBLP DOI BibTeX RDF
2	Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester	Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Hossein Asadi, Mehdi Baradaran Tahoori	Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Lianlian Zeng, Paul Beckett	Soft Error Rate Estimation in Deep Sub-micron CMOS.	PRDC	2007	DBLP DOI BibTeX RDF
2	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	On Accelerating Soft-Error Detection by Targeted Pattern Generation.	ISQED	2007	DBLP DOI BibTeX RDF
2	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Christian J. Hescott, Drew C. Ness, David J. Lilja	Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment.	DSD	2007	DBLP DOI BibTeX RDF
2	Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka	A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery.	DSN	2007	DBLP DOI BibTeX RDF
2	Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano	Case Study: Soft Error Rate Analysis in Storage Systems.	VTS	2007	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan	Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Sanjit A. Seshia, Wenchao Li, Subhasish Mitra	Verification-guided soft error resilience.	DATE	2007	DBLP DOI BibTeX RDF
2	Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski	Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Tino Heijmen	Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs.	IOLTS	2007	DBLP DOI BibTeX RDF
2	Franz X. Ruckerbauer, Georg Georgakos	Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.	IOLTS	2007	DBLP DOI BibTeX RDF	NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU
2	Yan Lin, Lei He	Device and architecture concurrent optimization for FPGA transient soft error rate.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Chong Zhao, Sujit Dey	Modeling soft error effects considering process variations.	ICCD	2007	DBLP DOI BibTeX RDF
2	Subhasish Mitra, Pia Sanda, Norbert Seifert	Soft Errors: Technology Trends, System Effects, and Protection Techniques.	IOLTS	2007	DBLP DOI BibTeX RDF	Memory soft errors, Logic soft errors, timing derating, logic derating, architectural derating, Built-In Soft Error Resilience, reliability, data integrity, availability, Error Correcting Codes, error detection, recovery, Soft errors, FITs, radiation hardening
2	Wangyuan Zhang, Xin Fu, Tao Li, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
2	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom-Based Soft Error Detection in Microprocessors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	Simulation, fault tolerance, fault injection, redundant design
2	Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González	Exploiting Narrow Values for Soft Error Tolerance.	Computer Architecture Letters	2006	DBLP DOI BibTeX RDF
2	Ming Zhang, Naresh R. Shanbhag	Soft-Error-Rate-Analysis (SERA) Methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Byonghyo Shim, Naresh R. Shanbhag	Energy-efficient soft error-tolerant digital signal processing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai	SEVA: A Soft-Error- and Variation-Aware Cache Architecture.	PRDC	2006	DBLP DOI BibTeX RDF
2	Dimitrios Bountas, Georgios I. Stamoulis	CARROT - A Tool for Fast and Accurate Soft Error Rate Estimation.	SAMOS	2006	DBLP DOI BibTeX RDF	simulation, combinational circuits, SER
2	Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim	Soft Error Resilient System Design through Error Correction.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Tino Heijmen, André Nieuwland	Soft-Error Rate Testing of Deep-Submicron Integrated Circuits.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	Cost-efficient soft error protection for embedded microprocessors.	CASES	2006	DBLP DOI BibTeX RDF	reliability, embedded processors, soft errors
2	Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian	Mitigating soft error failures for multimedia applications by selective data protection.	CASES	2006	DBLP DOI BibTeX RDF	horizontally partitioned caches, multimedia embedded systems, selective data protection, soft errors
2	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin	SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester	An efficient static algorithm for computing the soft error rates of combinational circuits.	DATE	2006	DBLP DOI BibTeX RDF
2	Riaz Naseer, Jeff Draper	DF-DICE: a scalable solution for soft error tolerant circuit design.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Hossein Asadi, Mehdi Baradaran Tahoori	Soft error hardening for logic-level designs.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Yoichi Sasaki, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
2	Tino Heijmen	Soft Error Rates in Deep-Submicron CMOS Technologies.	IOLTS	2006	DBLP DOI BibTeX RDF
2	André K. Nieuwland, Samir Jasarevic, Goran Jerin	Combinational Logic Soft Error Analysis and Protection.	IOLTS	2006	DBLP DOI BibTeX RDF
2	Rajeev R. Rao, David Blaauw, Dennis Sylvester	Soft error reduction in combinational logic using gate resizing and flipflop selection.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Hossein Asadi, Mehdi Baradaran Tahoori	Soft error derating computation in sequential circuits.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Srivathsan Krishnamohan, Nihar R. Mahapatra	Analysis and design of soft-error hardened latches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
2	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom Based Soft Error Detection in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
2	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.	VTS	2005	DBLP DOI BibTeX RDF
2	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee	Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits.	DATE	2005	DBLP DOI BibTeX RDF
2	Ghazanfar Asadi, Mehdi Baradaran Tahoori	An analytical approach for soft error rate estimation in digital circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto	A model of soft error effects in generic IP processors.	DFT	2005	DBLP DOI BibTeX RDF
2	Hossein Asadi, Mehdi Baradaran Tahoori	Soft Error Modeling and Protection for Sequential Elements.	DFT	2005	DBLP DOI BibTeX RDF
2	Jeetendra Kumar, Mehdi Baradaran Tahoori	A Low Power Soft Error Suppression Technique for Dynamic Logic.	DFT	2005	DBLP DOI BibTeX RDF
2	Robert C. Aitken, Betina Hold	Modeling Soft-Error Susceptibility for IP Blocks.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis	On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra	Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan	Impact of Soft Error Challenge on SoC Design.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt	The Soft Error Problem: An Architectural Perspective.	HPCA	2005	DBLP DOI BibTeX RDF
2	Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy	A Soft Error Monitor Using Switching Current Detection.	ICCD	2005	DBLP DOI BibTeX RDF
2	Robert Baumann	Soft Errors in Advanced Computer Systems.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	soft-error sensitivity, ground-level radiation mechanism, circuit operation, technology scaling