Search results for "soft processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jingzhao Ou, Viktor K. Prasanna	A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Exploration and Customization of FPGA-Based Soft Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Martin Labrecque, J. Gregory Steffan	Improving Pipelined Soft Processors with Multithreading.	FPL	2007	DBLP DOI BibTeX RDF
2	Jingzhao Ou, Viktor K. Prasanna	MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
2	Jingzhao Ou, Viktor K. Prasanna	COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors.	FCCM	2005	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan	Application-specific signatures for transactional memory in soft processors.	TRETS	2011	DBLP DOI BibTeX RDF
1	Kong Woei Susanto, Wayne Luk	Automating formal verification of customized soft-processors.	FPT	2011	DBLP DOI BibTeX RDF
1	Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto	Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth.	FCCM	2011	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	Design space exploration of instruction schedulers for out-of-order soft processors.	FPT	2010	DBLP DOI BibTeX RDF
1	Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan	Application-Specific Signatures for Transactional Memory in Soft Processors.	ARC	2010	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	An Efficient Non-blocking Data Cache for Soft Processors.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Monia Ghobadi, Martin Labrecque, Geoffrey Salmon, Kaveh Aasaraai, Soheil Hassas Yeganeh, Yashar Ganjali, J. Gregory Steffan	Caliper: a tool to generate precise and closed-loop traffic.	SIGCOMM	2010	DBLP DOI BibTeX RDF	traffic generation, soft processors, netfpga
1	Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis	A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.	DATE	2009	DBLP BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Fine-grain performance scaling of soft vector processors.	CASES	2009	DBLP DOI BibTeX RDF	VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
1	Danniel C. Lopes, Rafael Marrocos Magalhães, Jorge Dantas de Melo, Adrião Duarte Dória Neto	Implementation and Evaluation of Modular Neural Networks in a Multiple Processor System on Chip to Classify Electric Disturbance.	CSE	2009	DBLP DOI BibTeX RDF
1	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
1	Young-Su Kwon, Bontae Koo, Nak-Woong Eum	Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.	FPL	2008	DBLP DOI BibTeX RDF
1	Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto	HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Custom code generation for soft processors.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir	Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors.	FPL	2007	DBLP DOI BibTeX RDF
1	Christoforos Kachris, Stamatis Vassiliadis	A reconfigurable platform for multi-service edge routers.	SBCCI	2007	DBLP DOI BibTeX RDF	edge routers, FPGA, reconfigurable logic
1	Ari Kulmala, Erno Salminen, Timo D. Hämäläinen	Evaluating Large System-on-Chip on Multi-FPGA Platform.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
1	Jingzhao Ou, Viktor K. Prasanna	Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	FPGA, design space exploration, processor, cosimulation
1	Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown	A Multithreaded Soft Processor for SoPC Area Reduction.	FCCM	2006	DBLP DOI BibTeX RDF
1	J. Khan, R. Vemuri	Energy management for battery-powered reconfigurable computing platforms.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Alexandros C. Dimopoulos, Christos Pavlatos, Ioannis Panagopoulos, George K. Papakonstantinou	An Efficient Hardware Implementation for AI Applications.	SETN	2006	DBLP DOI BibTeX RDF
1	Jingzhao Ou, Viktor K. Prasanna	Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Jawad Khan, Ranga Vemuri	Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors