Search results for "speed binning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.	IOLTS	2005	DBLP DOI BibTeX RDF	Speed binning, delay measurement hardware, process variation
2	Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.	ITC	2004	DBLP DOI BibTeX RDF
2	Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.	MTV	2004	DBLP DOI BibTeX RDF
1	Sreejit Chakravarty	A Process Monitor Based Speed Binning and Die Matching Algorithm.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta	Variation-aware speed binning of multi-core processors.	ISQED	2010	DBLP DOI BibTeX RDF
1	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy	Profit Aware Circuit Design Under Process Variations Considering Speed Binning.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
1	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
1	Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin	Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	microarchitecture, process variability
1	Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary	Evaluating the effects of cache redundancy on profit.	MICRO	2008	DBLP DOI BibTeX RDF
1	Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia	Low-overhead design technique for calibration of maximum frequency at multiple operating points.	ICCAD	2007	DBLP DOI BibTeX RDF	frequency calibration, voltage sensitivity, dynamic voltage and frequency scaling, ring oscillator
1	Satish Sivaswamy, Kia Bazargan	Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary	Microarchitectures for Managing Chip Revenues under Process Variations.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy	Speed binning aware design methodology to improve profit under parameter variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Azadeh Davoodi, Ankur Srivastava	Variability driven gate sizing for binning yield optimization.	DAC	2006	DBLP DOI BibTeX RDF	speed binning, process variations, gate sizing
1	Mike Hutton, Yan Lin, Lei He	Placement and Timing for FPGAs Considering Variations.	FPL	2006	DBLP DOI BibTeX RDF
1	Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak	On Silicon-Based Speed Path Identification.	VTS	2005	DBLP DOI BibTeX RDF
1	Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen	On A Software-Based Self-Test Methodology and Its Application.	VTS	2005	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham	On-chip delay measurement for silicon debug.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design for testability, delay fault testing, silicon debug
1	Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra	Speed Clustering of Integrated Circuits.	ITC	2004	DBLP DOI BibTeX RDF
1	Bruce Cory, Rohit Kapur, Bill Underwood	Speed Binning with Path Delay Test in 150-nm Technology.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang	Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. (PDF / PS)	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Sreejit Chakravarty, Ankur Jain	Fault Models for Speed Failures Caused by Bridges and Opens.	VTS	2002	DBLP DOI BibTeX RDF
1	Kee Sup Kim, Rathish Jayabharathi, Craig Carstens	SpeedGrade: An RTL Path Delay Fault Simulator.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	S. Balajee, Ananta K. Majhi	Automated AC (Timing) Characterization for Digital Circuit Testing.	VLSI Design	1998	DBLP DOI BibTeX RDF	Timing Characterization, STIL, Setup and Hold Time