Search results for "standard scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
2	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
2	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
2	Yun Shao 0002, Irith Pomeranz, Sudhakar M. Reddy	Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	On clustering of undetectable transition faults in standard-scan circuits.	VTS	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On Common-Mode Skewed-Load and Broadside Tests.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi	Delay defect screening for a 2.16GHz SPARC64 microprocessor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	delay defect, microprocessor, screening, at-speed
1	Marcin Gomulkiewicz, Maciej Nikodem, Tadeusz Tomczak	Low-cost and Universal Secure Scan: a Design- Architecture for Crypto Chips.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
1	Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Scan Tests with Multiple Fault Activation Cycles for Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
1	Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar	Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.	DATE	2004	DBLP DOI BibTeX RDF
1	Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee	Embedded deterministic test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
1	Seongmoon Wang, Sandeep K. Gupta	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich	Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	store and generate schemes, BIST, test data compression, deterministic BIST
1	Gustavo R. Alves, Jose M. Martins Ferreira	From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1.	VTS	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A BIST Structure to Test Delay Faults in a Scan Environment.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Applying two-pattern tests using scan-mapping.	VTS	1996	DBLP DOI BibTeX RDF	scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
1	Hannes C. Wittmann, Manfred Henftling	Path delay ATPG for standard scan design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Prab Varma	On Path-Delay Testing in a Standard Scan Environment.	ITC	1994	DBLP DOI BibTeX RDF
1	Bill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk	Fastpath: A Path-Delay Test Generator for Standard Scan Designs.	ITC	1994	DBLP DOI BibTeX RDF
1	Sungho Kang, Wai-On Law, Bill Underwood	Path-Delay Fault Simulation for a Standard Scan Design Methodology.	ICCD	1994	DBLP BibTeX RDF
1	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology.	DAC	1991	DBLP DOI BibTeX RDF
1	C. Thomas Glover, M. Ray Mercer	A Method of Delay Fault Test Generation.	DAC	1988	DBLP BibTeX RDF