Search results for "static test compaction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Scan circuits, test application time, static test compaction
2	Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy	A Method of Static Test Compaction Based on Don't Care Identification.	DELTA	2002	DBLP DOI BibTeX RDF	Coloring Problem, Don't Care Identification, ATPG, Static Test Compaction
2	Irith Pomeranz, Sudhakar M. Reddy	Vector replacement to improve static-test compaction forsynchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	scan circuits, test application time, static test compaction
2	Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy	SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.	VTS	2000	DBLP DOI BibTeX RDF	Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction
2	Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo	Static test compaction for synchronous sequential circuits based on vector restoration.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Static test compaction for delay fault test sets consisting of broadside and skewed-load tests.	VTS	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static test compaction for diagnostic test sets of full-scan circuits.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration.	VLSI Design	2010	DBLP DOI BibTeX RDF	interconnect open faults, test generation, bridging faults, static test compaction
1	Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A dynamic test compaction procedure for high-quality path delay testing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait	Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Feng Shi, Yiorgos Makris	SPIN-PAC: test compaction for speed-independent circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait	Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Properties of Maximally Dominating Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz	Reverse-order-restoration-based static test compaction for synchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz	PROPTEST: a property-based test generator for synchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	synchronous sequential circuits, Static test compaction
1	Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy	On static test compaction and test pattern ordering for scan designs.	ITC	2001	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy	On Improving Static Test Compaction for Sequential Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita	Static test compaction for IDDQ testing of bridging faults in sequential circuits.	Systems and Computers in Japan	2000	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test-Point Insertion to Enhance Test Compaction for Scan Designs.	DSN	2000	DBLP DOI BibTeX RDF	Scan design, test-point insertion, static test compaction
1	Irith Pomeranz, Sudhakar M. Reddy	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	synchronous sequential circuits, test application time, Static test compaction
1	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
1	Irith Pomeranz, Sudhakar M. Reddy	VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.	DATE	1998	DBLP DOI BibTeX RDF	static test compaction synchronous sequential circuits
1	Irith Pomeranz, Sudhakar M. Reddy	Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	dynamic test compaction, synchronous sequential circuits, static test compaction
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation