Search results for "static-random access memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Yiming Li, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
2	Y. S. Yu, H. W. Kye, B. N. Song, S.-J. Kim, J.-B. Choi	A new multi-valued static random access memory (MVSRAM) with hybrid circuit consisting of single-electron (SE) and MOSFET.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Chen-Huan Chiang, Sandeep K. Gupta	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
2	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
1	Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto	Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Sreeharsha Tavva, Dhireesha Kudithipudi	Characterization of Variation Aware Nanoscale Static Random Access Memory Designs.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Sreeharsha Tavva, Dhireesha Kudithipudi	Variation tolerant 9T SRAM cell design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram
1	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
1	Nishith N. Desai, Jonathan R. Haigh, Lawrence T. Clark	Reducing process variation impact on replica-timed static random access memory sense timing.	Integration	2009	DBLP DOI BibTeX RDF
1	David Hentrich, Erdal Oruklu, Jafar Saniie	Performance evaluation of SRAM cells in 22nm predictive CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
1	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
1	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
1	Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark	LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
1	Zhiyu Liu, Volkan Kursun	High Read Stability and Low Leakage Cache Memory Cell.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yi Xu, Zhiqiang Gao, Xiangqing He	A Flexible Embedded SRAM IP Compiler.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Tamer Cakici, Keejong Kim, Kaushik Roy	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
1	Fei Li, Yan Lin, Lei He	Field Programmability of Supply Voltages for FPGA Power Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance Benefits of Monolithically Stacked 3-D FPGA.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Richard F. Hobson	A New Single-Ended SRAM Cell With Write-Assist.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark	Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
1	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
1	G. Razavipour, A. Motamedi, Ali Afzali-Kusha	WL-VC SRAM: a low leakage memory circuit for deep sub-micron design.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov	Fast detection of data retention faults and other SRAM cell open defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Nam Sung Kim, David Blaauw, Trevor N. Mudge	Quantitative analysis and optimization techniques for on-chip cache leakage power.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang	A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Navid Azizi, Farid N. Najm	An Asymmetric SRAM Cell to Lower Gate Leakage.	ISQED	2004	DBLP DOI BibTeX RDF
1	Byung Cheol Song, Kang Wook Chun	Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder.	IEEE Trans. Circuits Syst. Video Techn.	2004	DBLP DOI BibTeX RDF
1	L. T. Clark, M. Morrow, W. Brown	Reverse-body bias and supply collapse for low effective standby power.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Navid Azizi, Farid N. Najm, Andreas Moshovos	Low-leakage asymmetric-cell SRAM.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta	A Column-based Processing Array for High-speed Digital Image Processing.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Manish Pandey, Randal E. Bryant	Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja	The design of an SRAM-based field-programmable gate array. I. Architecture.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Manish Pandey, Randal E. Bryant	Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation.	CAV	1997	DBLP DOI BibTeX RDF
1	A. J. van de Goor	Using March Tests to Test SRAMs.	IEEE Design & Test of Computers	1993	DBLP DOI BibTeX RDF
1	Jeff L. Chu, Hamid R. Torabi, Fred J. Towler	A 128Kb CMOS static random-access memory.	IBM Journal of Research and Development	1991	DBLP BibTeX RDF
1	Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto	On Design of Multiple-Valued Static Random-Access-Memory.	ISMVL	1990	DBLP BibTeX RDF