Search results for "structured ASICS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).	FPGA	2010	DBLP DOI BibTeX RDF	structured asics, via programmable fabric
3	Herman Schmit, Amit Gupta, Radu Ciobanu	Placement challenges for structured ASICs.	ISPD	2008	DBLP DOI BibTeX RDF	field programmable gate arrays, placement, structured ASICs
2	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
2	Ashutosh Chakraborty, Anurag Kumar, David Z. Pan	RegPlace: a high quality open-source placement framework for structured ASICs.	DAC	2009	DBLP DOI BibTeX RDF	global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
2	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	Incremental placement for structured ASICs using the transportation problem.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
2	Behrooz Zahiri	Structured ASICs: Opportunities and Challenges.	ICCD	2003	DBLP DOI BibTeX RDF
1	Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai	Design and analysis of via-configurable routing fabrics for structured ASICs.	DATE	2012	DBLP BibTeX RDF
1	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs).	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin	Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen	Clock routing for structured ASICs with via-configurable fabrics.	ISQED	2010	DBLP DOI BibTeX RDF
1	Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge	Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.	FPL	2010	DBLP DOI BibTeX RDF
1	Yu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su	Via configurable three-input lookup-tables for structured ASICs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	via-configurable, layout, look-up-table, vlsi, structured ASIC
1	Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin	Power gating design for standard-cell-like structured ASICs.	DATE	2010	DBLP BibTeX RDF
1	Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin	Standard Cell Like Via-Configurable Logic Block for Structured ASICs.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique for Structured ASICs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam	Equivalence Verification of FPGA and Structured ASIC Implementations.	FPL	2007	DBLP DOI BibTeX RDF
1	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
1	Tianpei Zhang, Sachin S. Sapatnekar	Buffering global interconnects in structured ASIC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	R. Reed Taylor, Herman Schmit	Enabling energy efficiency in via-patterned gate array devices.	DAC	2004	DBLP DOI BibTeX RDF	VPGA, optimization, low-power, power, voltage scaling, structured ASIC
1	Deepak D. Sherlekar	Design considerations for regular fabrics.	ISPD	2004	DBLP DOI BibTeX RDF	structured ASIC, regular fabric
1	Raul Camposano	Will the ASIC survive?	SBCCI	2004	DBLP DOI BibTeX RDF
1	Mike Hutton	Advances and trends in FPGA design.	SBCCI	2004	DBLP DOI BibTeX RDF