Search results for "stuck-at faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive Bridging and Stuck-At Faults.	ITC	2003	DBLP DOI BibTeX RDF	Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation
3	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
3	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
2	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Osman Hasan, Naeem Abbasi, Sofiène Tahar	Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays.	IFM	2009	DBLP DOI BibTeX RDF
2	Fatih Kocan, Daniel G. Saab	Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Dynamic fault diagnosis, FPGA, Emulation, Stuck-at faults, Circuits, Gate-level
2	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Simulating Resistive-Bridging and Stuck-At Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya	On finding the minimum test set of a BDD-based circuit.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	binary decision diagram (BDD), multiplexors, network flow, stuck-at faults, VLSI testing
2	Jack R. Smith, Tian Xia, Charles E. Stroud	An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	stuck-at faults, bridging faults, delay faults
2	James Chien-Mo Li	Diagnosis of single stuck-at faults and multiple timing faults in scan chains.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Ralf Eickhoff, Ulrich Rückert	Tolerance of Radial Basis Functions Against Stuck-At-Faults.	ICANN	2005	DBLP DOI BibTeX RDF
2	Jia Di, Parag K. Lala, Dilip P. Vasudevan	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.	DFT	2005	DBLP DOI BibTeX RDF
2	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen	Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel	Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Space compaction, testing, stuck-at faults, system-on-a-chip
2	Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu	On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
2	Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty	Diagnostic simulation of stuck-at faults in sequential circuits using compact lists.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	stuck-at fault diagnosis, Fault simulation
2	Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu	Test Generation for Double Stuck-at Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
2	Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui	On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	fault compensation, fault tolerance, fuzzy control, stuck-at faults, on-line testing
2	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
2	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
2	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
2	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
2	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-Redundancy in Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines
2	Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko	On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
2	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu	A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.	VTS	1999	DBLP DOI BibTeX RDF
2	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
2	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
2	Irith Pomeranz, Sudhakar M. Reddy	Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	test generation, fault simulation, stuck-at faults, bridging faults, circuit partitioning
2	Peter A. Krauss, Andreas Ganz, Kurt Antreich	Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	fault parallelism, search space parallelism, sequential circuits, ATPG
2	Srikanth Venkataraman, W. Kent Fuchs	Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
2	Takehiro Ito, Itsuo Takanami	On fault injection approaches for fault tolerance of feedforward neural networks.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	snapping faults, learning cycle, ditribution of correlations, output neuron, fault tolerance, reliabilities, fault injection, stuck-at faults, computer simulation, learning algorithm, feedforward neural networks, feedforward neural nets, recognition rate, learning methods, internal structure
2	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Cellular automata for deterministic sequential test pattern generation.	VTS	1997	DBLP DOI BibTeX RDF	deterministic sequential test pattern generation, cellular automaton identification, hardware structure, area occupation, ASIC testing, evolutionary algorithm, cellular automata, BIST, fault coverage, stuck-at faults, FSM, deterministic automata
2	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
2	Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman	Diagnostic simulation of stuck-at faults in combinational circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution
2	Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs	Dynamic diagnosis of sequential circuits based on stuck-at faults.	VTS	1996	DBLP DOI BibTeX RDF	dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
2	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
2	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
2	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
2	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
2	Janusz A. Brzozowski, Kaamran Raahemifar	Testing C-elements is not elementary.	ASYNC	1995	DBLP DOI BibTeX RDF	C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence
2	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
2	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
2	S. Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
2	Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu	Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution
2	Michael S. Hsiao, Janak H. Patel	A new architectural-level fault simulation using propagation prediction of grouped fault-effects. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	architectural-level fault simulation, propagation prediction, grouped fault-effects, fault effects, intelligent propagation prediction, automated behavioral simulation, ALFSIM, Architectural Level Fault Simulation, gate level fault simulation, VLSI, fault diagnosis, circuit analysis computing, stuck at faults, integrated circuit design, deterministic algorithm, data types, symbolic data, architectural level
2	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
2	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
2	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
2	Andrej Zemva, Franc Brglez	Detectable perturbations: a paradigm for technology-specific multi-fault test generation.	VTS	1995	DBLP DOI BibTeX RDF	detectable perturbations, technology-specific multi-fault test generation, multiple bridging, open faults, single-output modules, multi-output modules, mutation faults, technology-mapped cells, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, stuck-at faults, cellular arrays, benchmark circuits, generic system
2	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
2	Wuudiann Ke, Premachandran R. Menon	Multifault and delay-fault testability of multilevel circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	testing, testability, delay-faults, multiple stuck-at faults
2	Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault	Use of Fault Dropping for Multiple Fault Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults
2	El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny	On the generation of test patterns for multiple faults.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	Combinational circuits, stuck-at faults, test pattern generation, multiple faults, fault analysis
2	Susanta Chakraborty, Debesh Kumar Das, Bhargab B. Bhattacharya	Logical redundancies in irredundant combinational circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	irredundancy, testing, Boolean functions, combinational circuits, stuck-at faults, fanouts
2	Charles E. Stroud, Ahmed E. Barbour	Testability and test generation for majority voting fault-tolerant circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
2	Sreejit Chakravarty, Harry B. Hunt III	On Computing Signal Probability and Detection Probability of Stuck-at Faults.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	pseudo gates, logic testing, built-in self test, combinational circuits, random testing, stuck-at faults, combinatorial circuits, testability analysis, detection probability, signal probability, pseudorandom testing, enumeration algorithm
2	Alexander Iosupovicz	Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	fault detection experiments, minimal test set, two-level logic, stuck-at faults, Bridge faults, unate functions
1	Irith Pomeranz	Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Carson Dunbar, Kundan Nepal	Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults.	JCP	2011	DBLP DOI BibTeX RDF
1	Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi	Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Robert A. Nawrocki, Richard M. Voyles	Artificial neural network performance degradation under network damage: Stuck-at faults.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Valentina Andreeva	Test minimization technique for multiple stuck-at faults of combinational circuit.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Output-Dependent Diagnostic Test Generation.	VLSI Design	2010	DBLP DOI BibTeX RDF	diagnostic test generation, stuck-at faults, full-scan circuits
1	Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang	Efficient diagnosis of scan chains with single stuck-at faults.	CISS	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Definition and application of approximate necessary assignments.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	necessary assignments, random test generation, test generation, stuck-at faults
1	Irith Pomeranz, Sudhakar M. Reddy	Partitioned n-detection test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
1	Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker	TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
1	Jan Schat	Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns.	DDECS	2008	DBLP DOI BibTeX RDF
1	Fei Wang, Yu Hu, Xiaowei Li	Adaptive Diagnostic Pattern Generation for Scan Chains.	DELTA	2008	DBLP DOI BibTeX RDF	very large scale integration (VLSI), testing, diagnosis, Boolean satisfiability, scan chain
1	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew	GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara	A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Pallav Gupta, Rui Zhang, Niraj K. Jha	Automatic Test Generation for Combinational Threshold Logic Networks.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Lei Fang, Michael S. Hsiao	Bilateral Testing of Nano-scale Fault-Tolerant Circuits.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Bilateral fault model, Fault-tolerant, ATPG, Nanoelectronics
1	Anjela Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikoleva	Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.	DFT	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
1	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test
1	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
1	Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek	A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet	Fault Tolerant CMOS Logic Using Ternary Gates.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Kim T. Le, Dong Hyun Baik, Kewal K. Saluja	Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha	Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
1	Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang	Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.	VTS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Invariant States and Redundant Logic in Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF