Search results for "sub-threshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun	A 2.6 µW sub-threshold mixed-signal ECG SoC.	ISLPED	2009	DBLP DOI BibTeX RDF	sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
4	Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun	Analyzing and modeling process balance for sub-threshold circuit design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	minimum energy operation, process balance, process imbalance, sub-threshold digital circuits, sub-threshold modeling
4	Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha Chandrakasan	Sub-threshold design: the challenges of minimizing circuit energy.	ISLPED	2006	DBLP DOI BibTeX RDF	low voltage memory, sub-threshold digital circuits, sub-threshold logic, process variations, dynamic voltage scaling
3	Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne Burleson	Low-power sub-threshold design of secure physical unclonable functions.	ISLPED	2010	DBLP DOI BibTeX RDF	embedded system security, sub-threshold circuits, RFID, physical unclonable function
3	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
3	Sudhanshu Khanna, Benton H. Calhoun	Serial sub-threshold circuits for ultra-low-power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	bit width, serial systems, leakage, ultra low power, sub-threshold
3	Joseph F. Ryan, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
3	Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Vt balancing and device sizing towards high yield of sub-threshold static logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	variability, sub-threshold
3	Joyce Kwong, Anantha P. Chandrakasan	Variation-driven device sizing for minimum energy sub-threshold circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	minimum energy point, sub-threshold circuits, delay model
3	Jonggab Kil, Jie Gu, Chris H. Kim	A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.	ISLPED	2006	DBLP DOI BibTeX RDF	capacitive boosting, sub-threshold circuit, clock skew, global interconnect, variation tolerance
3	Ik Joon Chang, Jae-Joon Kim, Kaushik Roy	Robust level converter design for sub-threshold logic.	ISLPED	2006	DBLP DOI BibTeX RDF	low power circuit design, sub-threshold logic, level converter
3	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
3	Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan	Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	sub-threshold leakage, CMOS, within-die variation
2	Basab Datta, Wayne Burleson	Temperature effects on energy optimization in sub-threshold circuit design.	ISQED	2009	DBLP DOI BibTeX RDF
2	Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya	Design and implementation of a sub-threshold BFSK transmitter.	ISQED	2009	DBLP DOI BibTeX RDF
2	Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello	New performance/power/area efficient, reliable full adder design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	d3l, reliability, dynamic, full-adder, sub-threshold
2	Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici	Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.	PATMOS	2008	DBLP DOI BibTeX RDF	Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations
2	Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Statistical noise margin estimation for sub-threshold combinational circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei	New technique in design of active rf cmos mixers for low flicker noise and high conversion gain.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	1.cmos mixer, direct conversion receiver, flicker noise, sub-threshold, ota, noise figure
2	Deyuan Xiao, Gary Chen, Roger Lee, Yung Liu, ChiCheong Shen	Planar split dual gate MOSFET.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	novel device, planar split dual gate, tunable sub-threshold swing, MOSFET
2	Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu	On Composite Leakage Current Maximization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage
2	Mini Nanua, David Blaauw	Investigating Crosstalk in Sub-Threshold Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
2	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
2	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
2	Jonathan Bentwich	The duality principle: irreducibility of sub-threshold psychophysical computation to neuronal brain activation.	Synthese	2006	DBLP DOI BibTeX RDF	Materialistic reductionism, Duality principle, Body-mind, Binding problem, Computation, Psychophysics, Neuroscience
2	Changbo Long, Jinjun Xiong, Yongpan Liu	Techniques of Power-gating to Kill Sub-Threshold Leakage.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
2	Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos, Dimitris K. Papakostas, C. A. Dimitriadis, Stilianos Siskos	Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri	A PLA based asynchronous micropipelining approach for subthreshold circuit design.	DAC	2006	DBLP DOI BibTeX RDF	micro-pipelining, asynchronous, PLA, sub-threshold
2	Armin Wellig, Julien Zory	Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Nikhil Jayakumar, Sunil P. Khatri	A variation tolerant subthreshold design approach.	DAC	2005	DBLP DOI BibTeX RDF	variation-toleran, self-adjusting, body-biasing, sub-threshold
2	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Post-layout leakage power minimization based on distributed sleep transistor insertion.	ISLPED	2004	DBLP DOI BibTeX RDF	sub-threshold current, leakage power, sleep transistor
2	Amit Agarwal, Kaushik Roy	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
2	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
2	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Robust ultra-low power sub-threshold DTMOS logic.	ISLPED	2000	DBLP DOI BibTeX RDF
2	Hendrawan Soeleman, Kaushik Roy	Digital CMOS logic operation in the sub-threshold region.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Jinn-Shyan Wang, Pei-Yao Chang, Chi-Chang Lin	Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Meeta Srivastav, Michael B. Henry, Leyla Nazhandali	Design of low-power, scalable-throughput systems at near/sub threshold voltage.	ISQED	2012	DBLP DOI BibTeX RDF
1	Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy	A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Kai Kinoshita, Hiroyuki Torikai	A Self-Organizing Pulse-Coupled Network of Sub-Threshold Oscillating Spiking Neurons.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell, Alexandre Yakovlev	Sub-threshold synchronizer.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Hui Shao, X. Li, Chi-Ying Tsui	Low energy multi-stage level converter for sub-threshold logic.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy	Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A 12.4μm2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Sandeep Sriram, Haiqing Nan, Ken Choi	Low power latch design in near sub-threshold region to improve reliability for soft error.	ISQED	2011	DBLP DOI BibTeX RDF
1	David Li, Pierce Chuang, David Nairn, Manoj Sachdev	Design and analysis of metastable-hardened flip-flops in sub-threshold region.	ISLPED	2011	DBLP BibTeX RDF
1	Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang	8T single-ended sub-threshold SRAM with cross-point data-aware write operation.	ISLPED	2011	DBLP BibTeX RDF
1	Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang	Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation.	ISLPED	2011	DBLP BibTeX RDF
1	Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens	Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder.	DSD	2011	DBLP DOI BibTeX RDF
1	Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez	Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.	DSD	2011	DBLP DOI BibTeX RDF
1	Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao	Robust design of sub-threshold flip-flop cells for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A 45.6μ2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Jun Zhou, Senthil Jayapal, Ben Busze, Li Huang, Jan Stuyt	A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library.	DAC	2011	DBLP DOI BibTeX RDF
1	Seokjoong Kim, Matthew R. Guthaus	Leakage-aware redundancy for reliable sub-threshold memories.	DAC	2011	DBLP DOI BibTeX RDF
1	Jun Zhou, Senthil Jayapal, Jan Stuyt, Jos Huisken, Harmke de Groot	The impact of inverse narrow width effect on sub-threshold device sizing.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Y. Joly, L. Truphemus, Laurent Lopez, Jean Michel Portal, Hassen Aziza, F. Julien, Pascal Fornara	Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Chenchang Zhan, Wing-Hung Ki	An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang	An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions.	SoCC	2011	DBLP DOI BibTeX RDF
1	Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato	A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization.	SoCC	2011	DBLP DOI BibTeX RDF
1	Alessandro Barenghi, Cédric Hocquet, David Bol, François-Xavier Standaert, Francesco Regazzoni, Israel Koren	Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation.	RFIDSec	2011	DBLP DOI BibTeX RDF
1	Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao	Detecting stability faults in sub-threshold SRAMs.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Hiroyuki Mino, Dominique M. Durand	Enhancement of information transmission of sub-threshold signals applied to distal positions of dendritic trees in hippocampal CA1 neuron models with stochastic resonance.	Biological Cybernetics	2010	DBLP DOI BibTeX RDF
1	Adelmo Ortiz-Conde, Francisco J. García-Sánchez, Juin J. Liou, Ching-Sung Ho	Integration-based approach to evaluate the sub-threshold slope of MOSFETs.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Mehrdad Hosseini Zadeh, David Wang, Eric Kubica	The effect of sub-threshold forces on human performance in multi-modal computer-aided design.	Computer-Aided Design	2010	DBLP DOI BibTeX RDF
1	Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy	Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Jun Zhou, Maryam Ashouei, David Kinniment, Jos Huisken, Gordon Russell	Extending Synchronization from Super-Threshold to Sub-threshold Region.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø	Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.	ASYNC	2010	DBLP DOI BibTeX RDF
1	Niklas Lotze, Jacob Göppert, Yiannos Manoli	Timing modeling for digital sub-threshold circuits.	DATE	2010	DBLP BibTeX RDF
1	Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph F. Ryan, Brian P. Otis	System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Chutham Sawigun, Dipankar Pal, Andreas Demosthenous	A wide-input linear range sub-threshold transconductor for sub-Hz filtering.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Matthias W. Blesken, Sven Lütkemeier, Ulrich Rückert	Multiobjective optimization for transistor sizing sub-threshold CMOS logic standard cells.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry	Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Mehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali	Sub-threshold charge recovery circuits.	ICCD	2010	DBLP DOI BibTeX RDF
1	Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal	Xetal-Pro: an ultra-low energy and high throughput SIMD processor.	DAC	2010	DBLP DOI BibTeX RDF	Xetal-Pro, hybrid memory system, SIMD, low-energy
1	Apisak Worapishet, Phanumas Khumsat	Analysis and Design of Sub-Threshold R-MOSFET Tunable Resistor.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Wei Bian, Jin He, Lining Zhang, Jian Zhang 0002, Mansun Chan	Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	S. Ramasamy, B. Venkataramani, P. Meenatchisundaram	A low power CMOS voltage reference circuit with sub threshold MOSFETs.	IJICT	2009	DBLP DOI BibTeX RDF
1	Mark Tuckwell, Christos Papavassiliou	An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Sudhanshu Khanna, Randy W. Mann, Jiajing Wang	Sub-threshold Circuit Design with Shrinking CMOS Devices.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock	Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Kanupriya Gulati, Sunil P. Khatri, Peng Li	Closed-loop modeling of power and temperature profiles of FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	sub-threshold leakage, dynamic power
1	Basab Datta, Wayne P. Burleson	Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sensor, interconnect, temperature, oscillator
1	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
1	Jader A. De Lima	A compact low-distortion low-power instrumentation amplifier.	SBCCI	2009	DBLP DOI BibTeX RDF	class-AB output stage, double-port amplifier, instrumentation amplifier
1	Kuande Wang, Li Chen, Jinsheng Yang	AN ultra low power fault tolerant SRAM design in 90nm CMOS.	CCECE	2009	DBLP DOI BibTeX RDF
1	Hongbo Zhou, Hong-Ju Yang, Haiyun Xu, Qiang Cheng	A New Computational Tool for the Post Session Analysis of the Prepulse Inhibition Test in Neural Science.	CSE	2009	DBLP DOI BibTeX RDF
1	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
1	S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya	100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta	Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.	NanoNet	2009	DBLP DOI BibTeX RDF	low-energy circuits, single electron transistors, binary decision diagram logic circuits
1	Omer Can Akgun, Yusuf Leblebici	Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta, R. S. Gupta	Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	Yink Khai Teh, Faisal Mohd-Yasin, Florence Choong, Mamun Bin Ibne Reaz	Design of adaptive supply voltage for sub-threshold logic based on sub-1 V bandgap reference circuit.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF