Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim	Utilizing reverse short channel effect for optimal subthreshold circuit design.	ISLPED	2006	DBLP DOI BibTeX RDF	PVT variations, reverse short channel effect, optimization, digital circuits, subthreshold circuits, subthreshold operation
4	Benton H. Calhoun, Anantha Chandrakasan	Characterizing and modeling minimum energy operation for subthreshold circuits.	ISLPED	2004	DBLP DOI BibTeX RDF	minimum energy point, subthreshold model, energy model, subthreshold circuits
3	Sumanth Amarchinta, Dhireesha Kudithipudi	Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	charge-boosters, subthreshold design, biasing
3	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
3	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
3	David Bol, Denis Flandre, Jean-Didier Legat	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive circuits, subthreshold logic, variability, CMOS digital integrated circuits, ultra-low power
3	Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
3	Lei Zhang, Zhiping Yu, Xiangqing He	A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors.	ISQED	2008	DBLP DOI BibTeX RDF	CMOS Process Fluctuations, Subthreshold Current Mirror, Discrete Martingale, Probability, Random Variable
3	Biswajit Mishra, Bashir M. Al-Hashimi	Subthreshold FIR Filter Architecture for Ultra Low Power Applications.	PATMOS	2008	DBLP DOI BibTeX RDF	Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR
3	Yuto Nakamura, Kazuhiro Tsuboi, Osamu Hoshino	Lateral Excitation between Dissimilar Orientation Columns for Ongoing Subthreshold Membrane Oscillations in Primary Visual Cortex.	ICANN	2008	DBLP DOI BibTeX RDF	Lateral excitation, Feature binding, Orientation map, Ongoing subthreshold membrane oscillation, Neural network model, Primary visual cortex
3	Michael B. Henry, Syed Imtiaz Haider, Leyla Nazhandali	A low-power parallel design of discrete wavelet transform using subthreshold voltage technology.	CASES	2008	DBLP DOI BibTeX RDF	low power, parallel, wavelet, subthreshold
3	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
3	Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang	Energy optimality and variability in subthreshold design.	ISLPED	2006	DBLP DOI BibTeX RDF	ultra-low energy, variability, subthreshold circuits
3	Jabulani Nyathi, Brent Bero	Logic circuits operating in subthreshold voltages.	ISLPED	2006	DBLP DOI BibTeX RDF	logic styles, medium-to-high speed, off current, ultra-low power, noise margins, subthreshold, body biasing
3	John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.	DAC	2006	DBLP DOI BibTeX RDF	subthreshold logic, ultra-low power design, logical effort
3	Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester	Analysis and mitigation of variability in subthreshold design.	ISLPED	2005	DBLP DOI BibTeX RDF	max of lognormal RVs, subthreshold variability
3	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
3	Luiz Alberto P. Melek, Márcio C. Schneider, Carlos Galup-Montoro	Body-bias compensation technique for SubThreshold CMOS static logic gates.	SBCCI	2004	DBLP DOI BibTeX RDF	body-bias compensation, static logic, low-power, CMOS, logic circuits, subthreshold
2	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
2	Hamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.	DAC	2010	DBLP DOI BibTeX RDF	energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation
2	Jeremy R. Tolbert, Saibal Mukhopadhyay	Accurate buffer modeling with slew propagation in subthreshold circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao	New subthreshold concepts in 65nm CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
2	Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	body bias clustering, performance compensation, layout, manufacturing variability, subthreshold circuits
2	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Michael B. Henry, Leyla Nazhandali	Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.	HiPEAC	2009	DBLP DOI BibTeX RDF
2	Snorre Aunet, Bengt Oelmann, P. A. Norseng, Yngvar Berg	Real-Time Reconfigurable Subthreshold CMOS Perceptron.	IEEE Transactions on Neural Networks	2008	DBLP DOI BibTeX RDF
2	John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
2	Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici	Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Belén Sancristóbal, José M. Sancho, Jordi García-Ojalvo	Resonant Spike Propagation in Coupled Neurons with Subthreshold Activity.	ICANN	2008	DBLP DOI BibTeX RDF
2	Ameet Chavan, Eric MacDonald, Norman Liu, Joseph Neff	A novel floating gate circuit family with subthreshold voltage swing for ultra-low power operation.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim	Circuit techniques for ultra-low power subthreshold SRAMs.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Rodrigo Jaramillo-Ramirez, Javid Jaffari, Mohab Anis	Variability-aware design of subthreshold devices.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Håvard Pedersen Alstad, Snorre Aunet	Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation.	DDECS	2008	DBLP DOI BibTeX RDF
2	Håvard Pedersen Alstad, Snorre Aunet	Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
2	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
2	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
2	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Tae-Hyoung Kim, John Keane, Hanyong Eom, Chris H. Kim	Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
2	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold Pass Transistor Logic for Ultra-Low Power Operation.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling Subthreshold Leakage Current in General Transistor Networks.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Jon Alfredsson, Snorre Aunet	Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw	Nanometer Device Scaling in Subthreshold Circuits.	DAC	2007	DBLP DOI BibTeX RDF
2	Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw	Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.	DAC	2007	DBLP DOI BibTeX RDF
2	Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min	Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Rodrigo Jaramillo-Ramirez, Mohab Anis	A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Snorre Aunet, Hans Kristian Otnes Berge	Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.	IWANN	2007	DBLP DOI BibTeX RDF
2	Niklas Lotze, Maurits Ortmanns, Yiannos Manoli	A Study on self-timed asynchronous subthreshold logic.	ICCD	2007	DBLP DOI BibTeX RDF
2	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
2	Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester	Energy efficient near-threshold chip multi-processing.	ISLPED	2007	DBLP DOI BibTeX RDF	near-threshold, energy efficient, CMP, subthreshold
2	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
2	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
2	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
2	Horacio G. Rotstein, Tim Oppermann, John A. White, Nancy Kopell	The dynamic structure underlying subthreshold oscillatory activity and the onset of spikes in a model of medial entorhinal cortex stellate cells.	Journal of Computational Neuroscience	2006	DBLP DOI BibTeX RDF	Reduction of dimensions, Canard, Generalized integrate-and-fire models, Theta rhythm, Hopf bifurcation
2	Akhilesh Kumar, Mohab Anis	Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance.	ISQED	2006	DBLP DOI BibTeX RDF
2	Domenik Helms, Marko Hoyer, Wolfgang Nebel	Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Domenik Helms, Günter Ehmen, Wolfgang Nebel	Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation.	ISLPED	2006	DBLP DOI BibTeX RDF	modeling, process variation, leakage, state dependence
2	Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai	A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Bo Fu, Paul Ampadu	Techniques for robust energy efficient subthreshold domino CMOS circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Jon Alfredsson, Bengt Oelmann	Capacitance selection for digital floating-gate circuits operating in subthreshold.	ISCAS	2006	DBLP DOI BibTeX RDF
2	David Blaauw, Bo Zhai	Energy efficient design for subthreshold supply voltage operation.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
2	Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud	An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage
2	Scott Hanson, Dennis Sylvester, David Blaauw	A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	voltage scaling, gate sizing, subthreshold circuits
2	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
2	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
2	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Bhavana Jharia, Sankar Sarkar, Rajendra Prasad Agarwal	Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET.	ISQED	2005	DBLP DOI BibTeX RDF
2	Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw	Energy Optimization of Subthreshold-Voltage Sensor Network Processors.	ISCA	2005	DBLP DOI BibTeX RDF
2	Hongchin Lin, Chao-Jui Liang	A sub-1V bandgap reference circuit using subthreshold current.	ISCAS	2005	DBLP DOI BibTeX RDF
2	K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, T. Sakurai	Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).	ISCAS	2005	DBLP DOI BibTeX RDF
2	Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar	Biasing techniques for subthreshold MOS resistive grids.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Walid Elgharbawy, Pradeep Golconda, Ashok Kumar, Magdy Bayoumi	A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jinhui Chen, Lawrence T. Clark, Yu Cao	Robust Design of High Fan-In/Out Subthreshold Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
2	Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy	A Feasibility Study of Subthreshold SRAM Across Technology Generations.	ICCD	2005	DBLP DOI BibTeX RDF
2	Paul Beckett	Low-power circuits using dynamic threshold devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	silicide, thin-body, CMOS, nanotechnology, SOI, subthreshold leakage, double-gate
2	Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi	Noise-tolerant high fan-in dynamic CMOS circuit design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits
2	Alexandre Valentian, Olivier Thomas, Andrei Vladimirescu, Amara Amara	Modeling subthreshold SOI logic for static timing analysis.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Volkan Kursun, Eby G. Friedman	Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.	ISQED	2004	DBLP DOI BibTeX RDF
2	L. Darrell Whitley, Keith Bush, Jonathan E. Rowe	Subthreshold-Seeking Behavior and Robust Local Search.	GECCO	2004	DBLP DOI BibTeX RDF
2	Walid Elgharbawy, Magdy A. Bayoumi	New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui.	ISVLSI	2004	DBLP DOI BibTeX RDF
2	A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz	Leakage current reduction by new technique in standby mode.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	subthreshold current, low power, leakage current, digital integrated circuits, static power
2	Gytis Svirskis, Ramana Dodla, John Rinzel	Subthreshold outward currents enhance temporal integration in auditory neurons.	Biological Cybernetics	2003	DBLP DOI BibTeX RDF
2	Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester	Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design.	ISQED	2003	DBLP DOI BibTeX RDF
2	Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.	ITC	2003	DBLP DOI BibTeX RDF
2	Matthias Frey, Hans-Andrea Loeliger, Felix Lustenberger, Patrick Merkli, Patrik Strebel	Analog-decoder experiments with subthreshold CMOS soft-gates.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Nazareth P. Castellanos, Francisco de Borja Rodríguez Ortiz, Pablo Varona	Stochastic Networks with Subthreshold Oscillations and Spiking Activity.	IWANN	2003	DBLP DOI BibTeX RDF
2	Saibal Mukhopadhyay, Kaushik Roy	Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, variability, Monte Carlo, threshold voltage, gate leakage, subthreshold leakage
2	Alice Wang, Anantha Chandrakasan, Stephen V. Kosonocky	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF
2	Reid R. Harrison	A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect.	ISCAS	2002	DBLP DOI BibTeX RDF
2	James Kao, Siva Narendra, Anantha Chandrakasan	Subthreshold leakage modeling and reduction techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
2	Kiyoo Itoh	Low-voltage memories for power-aware systems.	ISLPED	2002	DBLP DOI BibTeX RDF	DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing
2	David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar	Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited). (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	standby, GIDL, leakage, tunneling, subthreshold, current
2	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Robust subthreshold logic for ultra-low power operation.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel	Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS.	ARVLSI	2001	DBLP DOI BibTeX RDF
2	Vincent F. Koosh, Rodney M. Goodman	Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits.	ARVLSI	2001	DBLP DOI BibTeX RDF