Search results for "superscalar architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame	Modeling Assembly Instruction Timing in Superscalar Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
2	Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures
2	Avi Mendelson, Neeraj Suri	Designing High-Performance & Reliable Superscalar Architectures: The out of Order Reliable Superscalar (O3RS) Approach.	DSN	2000	DBLP DOI BibTeX RDF	Transient Errors/Recovery, Pipelines, Superscalar architectures
2	Josep-Lluis Larriba-Pey, Daniel Jiménez-González, Juan J. Navarro	An Analysis of Superscalar Sorting Algorithms on an R8000 Processor. (PDF / PS)	SCCC	1997	DBLP DOI BibTeX RDF	superscalar sorting algorithms, R8000 processor, in-memory sorting algorithms, Quick sort, Heap sort, Multiway merge, parallel algorithms, locality, superscalar architectures, Radix sort, Bucket sort
2	Eliseu M. Chaves Filho, Edil S. Tavares Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
1	Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski	Out-of-order issue logic using sorting networks.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits
1	Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh	On the potential of latency tolerant execution in speculative multithreading.	IFMT	2008	DBLP DOI BibTeX RDF	latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors
1	Zhonglei Wang, Antonio Sanchez, Andreas Herkersdorf	SciSim: a software performance estimation framework using source code instrumentation.	WOSP	2008	DBLP DOI BibTeX RDF	debugging information, software performance estimation, source code instrumentation, microarchitecture
1	Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary	Transparent control independence (TCI).	ISCA	2007	DBLP DOI BibTeX RDF	control independence, selective re-execution, selective recovery, checkpoints, branch prediction, speculation
1	Wangyuan Zhang, Xin Fu, Tao Li, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
1	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Luigi Carro	Transparent acceleration of data dependent instructions for general purpose processors.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Evaluation of a Low-Power Clock Distribution Network Based on EPIC.	NPC	2007	DBLP DOI BibTeX RDF
1	Tsai Chi Huang, Linda M. Wills, Roy W. Melton, Cecil O. Alford	Predicting communication protocol performance on superscalar architectures using instruction dependency.	Perform. Eval.	2006	DBLP DOI BibTeX RDF
1	Akira Nishida, Hisashi Kotakemori, Tamito Kajiyama, Akira Nukada	Poster reception - Scalable software infrastructure project.	SC	2006	DBLP DOI BibTeX RDF
1	Luiz Vinicius Marra Ribas, Ronaldo Augusto de Lara Goncalves	Evaluating Branch Prediction Using Two-Level Perceptron Table.	PDP	2006	DBLP DOI BibTeX RDF
1	Zenaide Carvalho da Silva, João Angelo Martini, Ronaldo Augusto Lara Gonçalves	Extending the PPM Branch Predictor.	PDP	2006	DBLP DOI BibTeX RDF
1	Guilherme Dal Pizzol, Philippe Olivier Alexandre Navaux	Branch Prediction Topologies for SMT Architectures.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
1	Won Woo Ro, Jean-Luc Gaudiot	A Low-Complexity Issue Queue Design with Speculative Pre-execution.	HiPC	2005	DBLP DOI BibTeX RDF
1	Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors	Architectural Support for Enhanced SMT Job Scheduling.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Marc Epalza, Paolo Ienne, Daniel Mlynek	Dynamic Reallocation of Functional Units in Superscalar Processors.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Leonid Oliker, Andrew Canning, Jonathan Carter, John Shalf, David Skinner, Stéphane Ethier, Rupak Biswas, M. Jahed Djomehri, Rob F. Van der Wijngaart	Evaluation of Cache-based Superscalar and Cacheless Vector Architectures for Scientific Computations.	SC	2003	DBLP DOI BibTeX RDF
1	Santithorn Bunchua, D. Scott Wills, Linda M. Wills	Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
1	Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain	HiDISC: A Decoupled Architecture for Data-Intensive Application.	IPDPS	2003	DBLP DOI BibTeX RDF	Memory access latency and Speculative pre-execution, Data prefetching, Data-intensive applications, Decoupled architecture
1	Haris Lekatsas, Wayne Wolf, Yuan Xie	Code Compression for VLIW Processors Using Variable-to-Fixed Coding.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
1	Resit Sendag, David J. Lilja, Steven R. Kunkel	Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions.	Euro-Par	2002	DBLP DOI BibTeX RDF
1	Victor V. Zyuban, Peter M. Kogge	Inherently Lower-Power High-Performance Superscalar Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Low power microarchitecture, multicluster architecture, energy-efficient configurations, energy models
1	Ioannis Vakalis	A Comparison Study of the Behavior of Equivalent Algorithms in Fault Injection Experiments in Parallel Superscalar Architectures.	SAFECOMP	2001	DBLP BibTeX RDF
1	Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt	Lifetime-Sensitive Modulo Scheduling in a Production Environment.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	register requirements, software pipelining, VLIW, instruction scheduling, loop scheduling, Fine grain parallelism, superscalar architectures
1	Mark N. Yankelevsky, Constantine D. Polychronopoulos	alpha-coral: a multigrain, multithreaded processor architecture.	ICS	2001	DBLP DOI BibTeX RDF	processor archietecture, multithreaded, parallelizing compiler
1	M. Anton Ertl, David Gregg	The Behavior of Efficient Virtual Machine Interpreters on Modern Architectures.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Victor V. Zyuban, Peter M. Kogge	Optimization of high-performance superscalar architectures for energy efficiency.	ISLPED	2000	DBLP DOI BibTeX RDF
1	Xianfeng Zhou, Margaret Martonosi	Augmenting Modern Superscalar Architectures with Configurable Extended Instructions.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
1	Tatiana Gadelha Serra dos Santos, Sergio Bampi	Analyzing Instruction Prefetch Schemes in Superscalar Architectures.	PDPTA	2000	DBLP BibTeX RDF
1	Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans	Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Dietmar Fey, Marko Degenkolb	Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits.	The Journal of Supercomputing	2000	DBLP DOI BibTeX RDF	optoelectronic VLSI, signed-digit arithmetic, pipeline processing, optical interconnects, superscalar architectures
1	Bernard K. Gunther	Facilitating Learning in Advanced Computer Architecture through Appropriate Simulation.	ACSC	2000	DBLP DOI BibTeX RDF
1	Sang Jeong Lee, Yuan Wang, Pen-Chung Yew	Decoupled Value Prediction on Trace Processors.	HPCA	2000	DBLP DOI BibTeX RDF	Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction
1	Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna	Performance of On-Chip Multiprocessors for Vision Tasks.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
1	Krishna M. Kavi, Hyong-Shik Kim, Joseph Arul, Ali R. Hurson	A Decoupled Scheduled Dataflow Multithreaded Architecture.	ISPAN	1999	DBLP DOI BibTeX RDF	Decoupling of memory access, Separate synchronization processor, Multithreaded architecture, Memory wall, Dataflow architecture
1	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
1	Esther Stümpel, Michael Thies, Uwe Kastens	VLIW Compilation Techniques for Superscalar Architectures.	CC	1998	DBLP DOI BibTeX RDF
1	Rafael R. dos Santos, Philippe Olivier Alexandre Navaux	Analysing a Multistreamed Superscalar Speculative Fetch Mechanism.	Euro-Par	1998	DBLP DOI BibTeX RDF
1	Eliseu M. Chaves Filho, Edil S. Tavares Fernandes	The Effect of the Speculation Depth on the Performance of Superscalar Architectures.	Euro-Par	1997	DBLP DOI BibTeX RDF
1	Andrew Davey, David Lloyd	An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures.	ICCD	1997	DBLP BibTeX RDF
1	Rastislav Bodík, Rajiv Gupta	Array Data Flow Analysis for Load-Store Optimizations in Superscalar Architectures.	LCPC	1995	DBLP DOI BibTeX RDF
1	Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald	Instruction Cache Fetch Policies for Speculative Execution.	ISCA	1995	DBLP DOI BibTeX RDF	C++
1	Mauricio J. Serrano, Wayne Yamamoto, Roger C. Wood, Mario Nemirovsky	A Model for Performance Estimation in a Multistreamed Superscalar Processor.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF