Search results for "superscalar machine"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	G. P. Jones, Nigel P. Topham	A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine.	MICRO	1997	DBLP BibTeX RDF	Access Decoupling, Superscalar, out of order execution, latency hiding
2	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
1	ElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham	Using Model Trees for Computer Architecture Performance Analysis of Software Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	superscalar machine, computer architecture performance analysis, tuning software, statistical regression modeling, M5' algorithm, SPEC CPU2006 suite, performance model tree, prefetching, software application
1	Seong-Won Lee, Jean-Luc Gaudiot	Throttling-Based Resource Management in High Performance Multithreaded Architectures.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Resource management, power management, multithreading, resource utilization, throttling
1	Won Woo Ro, Jean-Luc Gaudiot	Design and Effectiveness of Small-Sized Decoupled Dispatch Queues.	Euro-Par	2006	DBLP DOI BibTeX RDF
1	Jessica H. Tseng, Krste Asanovic	A Speculative Control Scheme for an Energy-Efficient Banked Register Fil.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	speculative control, Low-power, superscalar, register file, simultaneous multithreading
1	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt	Microarchitectural support for precomputation microthreads.	MICRO	2002	DBLP DOI BibTeX RDF
1	Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana	The MOLEN rho-mu-Coded Processor.	FPL	2001	DBLP DOI BibTeX RDF
1	Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen	Efficacy and Performance Impact of Value Prediction.	IEEE PACT	1998	DBLP DOI BibTeX RDF	usefulness tracking, instruction level parallelism, speculative execution, superscalar processor, value prediction, hybrid predictor
1	Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya	Performance Comparison of ILP Machines with Cycle Time Evaluation.	ISCA	1996	DBLP DOI BibTeX RDF
1	Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich	Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries.	MICRO	1996	DBLP BibTeX RDF	instruction-level parallel processors, latency constraint propagation, compiler optimization, instruction scheduling, global scheduling
1	Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv	VLIW Compilation Techniques in a Superscalar Environment.	PLDI	1994	DBLP DOI BibTeX RDF	profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000
1	Norman P. Jouppi	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1