Search results for "switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Jin Li, Chuan-lin Wu	A modular growth architecture for an ATM switch.	ICCCN	1995	DBLP DOI BibTeX RDF	modular growth architecture, growable ATM switch architecture, large scale ATM switch, switch size, nonuniform modular growth ATM switch, knockout switch, internal traffic, nonuniform concentration, connection pattern, performance, delay, throughput, telecommunication traffic
5	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
5	Daqing Xu, Hisao Kameda	Friend Pointer Registration Strategy and Its Scheme for Mobile Location Management.	AINA Workshops	2007	DBLP DOI BibTeX RDF	mobile tracking, mobile locating, old switch, new switch, home switch, friend switch, friend pointer, friend node and neighborhood, FPRMP
5	Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang	Generic Universal Switch Blocks.	ICCD	1999	DBLP DOI BibTeX RDF	HFPGA, logic block, switch block, programmable switch, universal switch block, dimension constraint, FPGA, routing, flexibility, routability
5	Parimal Patel, Saad Zahid	Design Considerations in an ATM Switch Design.	ICCCN	1998	DBLP DOI BibTeX RDF	ATM switch design, packet switching, ATM Switch, Switch architecture
5	Robert R. Henry 0002	A multicast ATM switch with slotted ring fabric.	ICCCN	1997	DBLP DOI BibTeX RDF	multicast ATM switch, slotted ring fabric, slotted ring ATM switch architecture, optical fiber switch, deterministic performance analysis equations, delay performance, zero blocking performance, 150 Mbit/s, asynchronous transfer mode, switching fabric
5	Syed Sohel Hussain, Yih-Chyun Jenq	Analysis and Optimization of a Banyan-Based ATM Switch by Simulations. (PDF / PS)	LCN	1996	DBLP DOI BibTeX RDF	Banyan based ATM switch, switch optimization, switch analysis, delay variance, performanc analysis, uniform traffic, three-state model, nonblocking first stage, packet blocking, enhanced priority scheme, single buffer Banyan network, double buffer switching element, delay sensitive voice packet, asynchronous transfer mode, asynchronous transfer mode, delay, throughput, bandwidth, simulation results, voice traffic, data traffic
5	A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
5	Chao-Ju Hou, Ching-Chih Han, Wun-Chun Chau	Priority-based high-speed switch scheduling for ATM networks. (PDF / PS)	LCN	1995	DBLP DOI BibTeX RDF	iterated switching networks, priority-based high-speed switch scheduling, AN2 switch, parallel iterative matching algorithm, maximal input-output matching, priority lists, input/output pairs, probability analysis, switch size, high QoS requirements, simulation, scheduling, parallel algorithms, computational complexity, asynchronous transfer mode, probability, local area networks, iterative methods, time complexity, ATM networks, iterations, switches, high-performance distributed computing
5	Sushil Aryal, James S. Meditch	Design of a large ATM switch with trunk grouping.	ICCCN	1995	DBLP DOI BibTeX RDF	load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss
4	Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu	Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	reconfigurable interconnection network, switch block, hyperuniversal, FPGA, universal, switch box
4	Hyoung-Il Lee, Seung-Woo Seo	Matching output queueing with a multiple input/output-queued switch.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	combined input/output-queued (CIOQ) switch, multiple input/output-queued (MIOQ) switch, output queueing emulation, parallel switching architecture
4	Afshin Shiravi, Paul S. Min, Yoon G. Kim	Traffic Dispatching Algorithm in Three-Stage Switch.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF	three-stage switch, sequence preserving, load balancing, Packet switch
4	Hongbing Fan, Yu-Liang Wu	Crossbar based design schemes for switch boxes and programmable interconnection networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
4	Deng Pan, Yuanyuan Yang	FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	virtual output queued (VOQ) switch, head of line (HOL) blocking, scheduling, Multicast, crossbar switch, multicast switch
4	Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong	Reduction design for generic universal switch blocks.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA architecture design, routing requirement, switch module, universal switch block, routing, decomposition
4	Josef Giglmayr	All-optical multi-layer switching architectures: (I) MxN-gon prism switches.	ICCCN	1998	DBLP DOI BibTeX RDF	Optical waveguide, 2x2-switch, directional coupler, Mach-Zehnder interferometer, cycle structure, logical switch architecture, physical switch, all-optical 3-D grid, grid size, mapping, connectivity, multi-layer
4	Erol Basturk, Alexander Birman, G. Delp, Roch Guérin, R. Haas, Sanjay Kamat, Dilip D. Kandlur, P. Pan, Dimitrios E. Pendarakis, Vinod G. J. Peris, Raju Rajan, Debanjan Saha, D. Williams	Design and implementation of a QoS capable switch-router.	ICCCN	1997	DBLP DOI BibTeX RDF	QoS capable switch-router, core ATM switch fabric, intelligent adapters, RSVP signalling, prototype network, UNIX hosts, network performance measurements, Internet, Internet, design, architecture, resource management, implementation, service differentiation, high throughput, IETF, control engine
4	Mingyao Yang, Lionel M. Ni	Design of Scalable and Multicast Capable Cut-Through Switches for High-Speed LANs. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	Intra-switch interconnect, Switch packaging, Multicast, Deadlock-free routing, Switch architecture, Cut-through switching
4	Keun-Bae Kim, Hyup-Jong Kim	Back-Pressure Buffering Scheme to Improve the Cell Loss Property on the Output Buffered ATM Switch. (PDF / PS)	LCN	1996	DBLP DOI BibTeX RDF	back-pressure buffering, cell loss property, output buffered ATM switch, input cells, push-out mechanism, selective pressure mechanism, small sized memory, asynchronous transfer mode, shared memory, queueing theory, simulation results, computer simulation, performance comparison, FIFO, switch fabric, output buffer
4	Jin Li	An output-shared buffer ATM switch. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	buffer ATM switch, output-shared, lower bandwidth, asynchronous transfer mode, ATM switch, buffer utilization
4	Byoung-Seok Park, Sung-Chun Kim	Design and Analysis of a New Fast Packet Switching Fabric Supporting Multimedia Traffic. (PDF / PS)	LCN	1996	DBLP DOI BibTeX RDF	fast packet switching fabric, ATM switch architecture, output queueing, switch analysis, FAB Banyan switching fabrics, Batcher sorter, double shuffle network, packet distributors, FAB networks, output buffer modules, compressed video data, performance evaluation, throughput, packet switching, hardware implementation, voice, multimedia traffic, packet delay, switch design, packet loss probability, text data
4	Wilbert H. F. J. Körver	A universal formalization of the effects of threshold voltages for discrete switch-level circuit models.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	field effect transistor switches, threshold voltage effects, discrete switch-level circuit models, universal formalization, switch imperfection, CMOS design, demolition degree, CMOS digital integrated circuits, state transitions, integrated circuit modelling, switching circuits
4	Latha A. Kant, William H. Sanders	Loss process analysis of the knockout switch using stochastic activity networks.	ICCCN	1995	DBLP DOI BibTeX RDF	loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability
4	A. Agrawal, Magdy A. Bayoumi, A. Elchouemi	A new ATM congestion control scheme for shared buffer switch architectures.	ICCCN	1995	DBLP DOI BibTeX RDF	pre-emptive congestion control scheme, shared buffer switch architectures, rate-based feedback scheme, guaranteed service traffic, continuous bit-rate traffic, leaky bucket mechanism, backward explicit congestion notification feedback scheme, mean inter-arrival time, buffer threshold throttle factor, cell reject throttle factor, rate reduction delta, transient behaviour, filter time, asynchronous transfer mode, ATM networks, simulation model, ATM switch, dynamic bandwidth allocation, best-effort traffic, variable bit-rate traffic, predictive scheme
4	Y. Chang, Nada Golmie, David H. Su	Study of interoperability between EFCI and ER switch mechanisms for ABR traffic in an ATM network.	ICCCN	1995	DBLP DOI BibTeX RDF	ABR traffic, rate-based flow control, transmission rate control, feedback information, resource management cells, network switching nodes, ATM Forum Traffic Management Specification, network switch mechanism, ATM switch vendor, bandwidth allocation fairness, explicit forward congestion indication, explicit rate mechanism, end system behavior, congestion notification, algorithms, interoperability, asynchronous transfer mode, asynchronous transfer mode, ATM network, simulation results, network performance, simulation study, performance characteristics, available bit rate, destination nodes
4	Peter Lidén, Peter Dahlgren	Switch-level modeling of transistor-level stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	transistor-level stuck-at faults, switch-level algorithms, fault modeling capability, fault detection measures, confidence degradation, unknown output values, uncertainty quantification, node model, fault diagnosis, logic testing, integrated circuit testing, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, switch-level modeling
4	Jin Li, Chuan-lin Wu	A novel architecture for an ATM switch. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	multicast function, shared-buffer ATM switch, first-in and first-out shared buffer, FIFO address queue, cell-loss performance, performance evaluation, asynchronous transfer mode, ATM switch, B-ISDN, control logic, buffer utilization
4	Steven E. Butner, David A. Skirmont	Architecture and design of a 40 gigabit per second ATM switch. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture
3	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
3	Boris Nechaev, Vern Paxson, Mark Allman, Andrei Gurtov	On calibrating enterprise switch measurements.	Internet Measurement Conference	2009	DBLP DOI BibTeX RDF	network traces, switch-based packet capture, trace calibration, enterprise networks
3	Saad Mneimneh	Matching from the first iteration: an iterative switching algorithm for an input queued switch.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	iterative switching algorithms, number of iterations, speedup, matching algorithms, input queued switch
3	Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee	Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	VLIW DSP processor, optimizing context switch overhead, microkernel design
3	Joe Kelly, Dean Nicholson, Edwin Lowery, Victor Grothen	Light-Enhanced FET Switch Improves ATE RF Power Settling.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	FET, RF switch, power settling, HVM, high-volume manufacturing, ATE, test time, settling time
3	Xiumin Gao	Tunable Optical Trap Induced by Focal Shift and Focal Switch in a Focusing Apodized Optical System.	BMEI	2008	DBLP DOI BibTeX RDF	optical trap, focal shift, focal switch, apodizer
3	Yan Wang, Zhiwen Bai, Miao Zhang, Wen Du, Ying Qin, Xiyang Liu	Fitness calculation approach for the switch-case construct in evolutionary testing.	GECCO	2008	DBLP DOI BibTeX RDF	switch-case construct, fitness function, evolutionary testing
3	Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker	Characterizing and modeling the behavior of context switch misses.	PACT	2008	DBLP DOI BibTeX RDF	context switch misses, stack distance profiling, prefetching, analytical model
3	Juan José Jaramillo, Fabio Milan, R. Srikant	Padded frames: a novel algorithm for stable scheduling in load-balanced switches.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	Birkhoff-von Neumann switch, load-balanced switch, scheduling
3	Ron Gabor, Shlomo Weiss, Avi Mendelson	Fairness enforcement in switch on event multithreading.	TACO	2007	DBLP DOI BibTeX RDF	SOE, Switch on Event multithreading, coarse-grained multithreading, weighted speedup, performance, fairness, throughput, multithreading
3	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang 0011, Michael Orshansky	Architecting a reliable CMP switch architecture.	TACO	2007	DBLP DOI BibTeX RDF	CMP switch, reliability, defect-tolerance
3	Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung	The exact channel density and compound design for generic universal switch blocks.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	universal switch block, routing algorithm, FPGA architecture
3	Miklos Kozlovszky, Tibor Berceli, Viktor Kozlovszky	NSOSS: the non-synchronized optical switch simulator.	VALUETOOLS	2007	DBLP DOI BibTeX RDF	DWDM, all-optical packet switch, discrete event simulation
3	Bill Lin, Isaac Keslassy	Frame-aggregated concurrent matching switch.	ANCS	2007	DBLP DOI BibTeX RDF	100% throughput, concurrent matching switch, frame scheduling, load-balanced router, packet switching
3	Timothy J. Brothers, Suresh Muknahallipatna, Jerry C. Hamann	Fibre Channel Switch Modeling at Fibre Channel-2 Level for Large Fabric Storage Area Network Simulations using OMNeT++: Preliminary Results.	LCN	2007	DBLP DOI BibTeX RDF	FC-2 level, Simulator, Modeling, Scaling, Switch, Fabric, Fibre Channel
3	Katsuya Watabe, Tetsuya Saito, Nobutaka Matsumoto, Takuo Tanemura, Hideaki Imaizumi, Abdullah Al Amin, Mitsuru Takenaka, Yoshiaki Nakano, Hiroyuki Morikawa	80Gb/s Multi-wavelength Optical Packet Switching Using PLZT Switch.	ONDM	2007	DBLP DOI BibTeX RDF	multi-wavelength, optical packet, PLZT switch, WDM
3	O. Zouraraki, Paraskevas Bakopoulos, K. Vyrsokinos, Hercules Avramopoulos	2x2 Bismuth-Oxide-Fiber Based Crossbar Switch for All-Optical Switching Architectures.	ONDM	2007	DBLP DOI BibTeX RDF	Optically controlled 2x2 switch, Bismuth Oxide Nonlinear fiber, Ultrafast Nonlinear Interferometer (UNI), all-optical signal processing
3	Francis M. David, Jeffrey C. Carlyle, Roy H. Campbell	Context switch overheads for Linux on ARM platforms.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF	context switch overhead, operating system
3	Chuanpeng Li, Chen Ding, Kai Shen	Quantifying the cost of context switch.	Experimental Computer Science	2007	DBLP DOI BibTeX RDF	context switch, cache interference
3	Cory Hawkins, Benjamin A. Small, D. Scott Wills, Keren Bergman	The Data Vortex, an All Optical Path Multicomputer Interconnection Network.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Optical switch fabrics, photonic packet switch, data vortex switch architecture, packet switching, optical switching
3	Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer	A Network Processor-Based, Content-Aware Switch.	IEEE Micro	2006	DBLP DOI BibTeX RDF	content-aware switch, ENP2611, Intel IXP 2400, network processor
3	Wenjie Li, Bin Liu 0001, Yang Xu, Heng Liao	Parallel Switch System with QoS Guarantee for Real-Time Traffic.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	QoS, load-balancing, parallel, priority, switch system
3	Iñigo Artundo, D. Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont	Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.	ISPA Workshops	2006	DBLP DOI BibTeX RDF	interconnection network, multiprocessors, Reconfiguration, distributed shared memory, context switch
3	Gaspar Mora, Jose Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne	Towards an efficient switch architecture for high-radix switches.	ANCS	2006	DBLP DOI BibTeX RDF	arbiter efficiency, partitioned crossbar, switch organization
3	Christoforos Kachris, Stamatis Vassiliadis	Design of a web switch in a reconfigurable platform.	ANCS	2006	DBLP DOI BibTeX RDF	web switch, reconfigurable logic
3	Hagit Attiya, David Hay, Isaac Keslassy	Packet-mode emulation of output-queued switches.	SPAA	2006	DBLP DOI BibTeX RDF	CIOQ switch, output-queued, packet-mode scheduling, switch emulation, packet switching, queuing delay
3	Jenhui Chen, Ai-Chun Pang, Shiann-Tsong Sheu, Hsueh-Wen Tseng	High Performance Wireless Switch Protocol for IEEE 802.11 Wireless Networks.	MONET	2005	DBLP DOI BibTeX RDF	wireless, MAC, ad hoc, infrastructure, switch, CSMA/CA
3	Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili	Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	link/switch scheduling, Quality of Service (QoS), LANs, switch architecture, cluster networks
3	David Er-El, Dror G. Feitelson	Communication Models for a Free-Space Optical Cross-Connect Switch.	The Journal of Supercomputing	2004	DBLP DOI BibTeX RDF	electroholographic switch, spanning topology, collision avoidance, circuit switching, forwarding, all-optical network, broadcast algorithm
3	John Mason	Teaching by analogy: the switch statement.	SIGCSE Bulletin	2004	DBLP DOI BibTeX RDF	methodology, switch, analogy
3	Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu	On Optimal Irregular Switch Box Designs.	FPL	2004	DBLP DOI BibTeX RDF	FPGA, Configurable computing, on-chip network, switch box
3	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
3	Hongbing Fan, Jiping Liu, Yu-Liang Wu	General Models and a Reduction Design Technique for FPGA Switch Box Designs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	hyper-universal, FPGA, global routing, detailed routing, reduction technique, optimum design, switch box
3	Sundar Iyer, Nick McKeown	Analysis of the parallel packet switch architecture.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	output queueing, load balancing, packet switch, Clos network, inverse multiplexing
3	Man Chi Chan, Tony T. Lee	Statistical performance guarantees in large-scale cross-path packet switch.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	cross-path switch, exponential bounded burstiness (EBB) processes, path switching, semioptical network, statistical performance guarantees, token assignment algorithm, quality of service (QoS), clos network, service curves
3	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	Concurrent fault detection for a multiple-plane packet switch.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	parallel planes, fault detection, packet switch, concurrent testing, single fault
3	H. S. Laskaridis, Georgios I. Papadimitriou, Andreas S. Pomportsis	Applying Optical Reconfiguration on ATM Switch Fabrics.	IPDPS	2003	DBLP DOI BibTeX RDF	ATM, reconfiguration, correlation, switch fabric
3	Ali Reza Ejlali, Seyed Ghassem Miremadi	Switch-level emulation.	DAC	2003	DBLP DOI BibTeX RDF	FPGA chips, gate-level models, emulation, switch-level models
3	Jan-Jan Wu, Da-Wei Wang, Yih-Fang Lin	Placement of I/O servers to improve parallel I/O performance on switch-based clusters.	ICS	2003	DBLP DOI BibTeX RDF	part-time I/O assignment, switch-based clusters, parallel I/O, bipartite matching
3	Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
3	Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda	HIPIQS: A High-Performance Switch Architecture Using Input Queuing.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	switch/router design, interconnection networks, parallel architectures, networks of workstations, high-speed interconnects
3	Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang	Comment on Generic Universal Switch Blocks.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	universal switch block design, Field programmable gate array, FPGA routing
3	Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik	An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	TAM switch, system-on-chip, interconnect testing
3	Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili	Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Quality of Service, multimedia communications, router architecture, switch scheduler
3	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
3	David Whelihan, Herman Schmit	Memory optimization in single chip network switch fabrics.	DAC	2002	DBLP DOI BibTeX RDF	network switch, SOC, memory optimization
3	Simon Jolly, Atanas N. Parashkevov, Tim McDougall	Automated equivalence checking of switch level circuits .	DAC	2002	DBLP DOI BibTeX RDF	MOS circuits, custom design, switch level analysis, formal verification, VLSI design, equivalence checking
3	Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul	System-Level Modeling of a Network Switch SoC.	ISSS	2002	DBLP DOI BibTeX RDF	memory visualization level design, network switch, computer-aided design, performance modeling, system modeling
3	Eiji Oki, Zhigang Jing, Roberto Rojas-Cessa, H. Jonathan Chao	Concurrent round-robin-based dispatching schemes for Clos-network switches.	IEEE/ACM Trans. Netw.	2002	DBLP DOI BibTeX RDF	Clos-network switch, throughput, packet switch, arbitration, dispatching
3	Ram Kesavan, Dhabaleswar K. Panda	Efficient Multicast on Irregular Switch-Based Cut-Through Networks with Up-Down Routing.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	cut-through routing, multicast, broadcast, wormhole routing, collective communication, networks of workstations, Parallel computer architecture, irregular networks, switch-based networks
3	Vincent W. S. Wong, Mark E. Lewis, Victor C. M. Leung	Stochastic control of path optimization for inter-switch handoffs in wireless ATM networks.	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	connection rerouting, inter-switch bandoff, path optimization, wireless ATM
3	Apostolos Dollas, Nikolaos Aslanides, Stamatios Kavvadias, Euripides Sotiriades, Kyprianos Papademetriou, Dionisios N. Pnevmatikatos	Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF	design core, reconfigurable computing, rapid prototyping, Active networks, ATM switch
3	F. Boujdaine, Z. Echchelh, Noufissa Mikou	Performance Studies of a Priority Switching Strategy in an All Optical Packet Switch. (PDF / PS)	LCN	2001	DBLP DOI BibTeX RDF	All-Optical packet switch, FLBM, Priorit y switching strategy, WDM
3	Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda	Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact.	IEEE Trans. Parallel Distrib. Syst.	2000	DBLP DOI BibTeX RDF	switch/router architecture, performance evaluation, multicast, interconnection networks, broadcast, collective communication, wormhole switching, Parallel computer architecture, cut-through switching
3	Damon S. Love, Sudhakar Yalamanchili, José Duato, Blanca Caminero, Francisco J. Quiles	Switch Scheduling in the Multimedia Router (MMR). (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	Quality of Service (QoS), Multimedia traffic, Router architecture, Switch scheduling
3	Marius Pirvu, Nan Ni, Laxmi N. Bhuyan	Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	input buffer management, CC-NUMA multiprocessors, performance evaluation, arbitration, execution driven simulation, switch design
3	Sangman Bak, Albert Mo Kim Cheng, Jorge Arturo Cobb, Ernst L. Leiss	Load-Balanced Routing and Scheduling for Real-Time Traffic in Packet-Switch Networks. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	load-balanced routing, shortest-path routing protocols, least-laxity scheduling algorithm, scheduling, protocols, computer networks, computer networks, packet switching, routing algorithm, scheduling algorithm, buffer overflow, telecommunication network routing, telecommunication traffic, packet loss, time-delay, packet-switch networks, end-to-end delay, bottlenecks, real-time traffic, network throughput, traffic load, data packets
3	Jonathan C. L. Liu, Lin Xia, David Hung-Chang Du, Rose P. Tsang, Allalaghatta Pavan	Scheduling Algorithms for A High-Speed Switch Supporting Real-Time Periodic Traffic Sources. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	high-speed switch, real-time periodic traffic sources, fast scheduling algorithms, periodic source flows, real-time delivery requirements, data frames, FCFS algorithm, CBR flows, variable bandwidth requirements, scheduling, real-time systems, packet switching, scheduling algorithms, wide area networks, WAN, telecommunication traffic, multiplexing, mission critical systems, constant bit rate
3	Abdel Ejnioui, N. Ranganathan	Routing on Switch Matrix Multi-FPGA Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	switch routing, Field programmable arrays, Multi-FPGA systems, Global routing, FPGA architecture, Interconnection structure
3	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
3	Olav Lysne	Deadlock Avoidance for Switches Based on Wormhole Networks. (PDF / PS)	ICPP	1999	DBLP DOI BibTeX RDF	Inter-switch deadlocks, Interconnect networks, Wormhole routing, Deadlock avoidance, Switch fabric
3	Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee	ATM switch design by high-level modeling, formal verification and high-level synthesi.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	verification, synthesis, ATM switch, high-level design
3	William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland	A FIFO Data Switch Design Experiment.	ASYNC	1998	DBLP DOI BibTeX RDF	Data Switch, P**3, Asynchronous, FIFO
3	Rajeev Sivaram, Ram Kesavan, Dhabaleswar K. Panda, Craig B. Stunkel	Where to Provide Support for Efficient Multicasting in Irregular Networks: Network Interface or Switch? (PDF / PS)	ICPP	1998	DBLP DOI BibTeX RDF	cut-through routing, performance evaluation, multicast, broadcast, collective communication, Parallel computer architecture, irregular networks, switch-based networks
3	Lluis Ribas, Jordi Carrabina	On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits.	DATE	1998	DBLP DOI BibTeX RDF	incremental simulation, switch-level circuit analysis, symbolic circuit traversal
3	George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis	Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control
3	Michael Jurczyk	Performance and Implementation Aspects of Higher Order Head-of-Line Blocking Switch Boxes. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	central memory buffering, higher order blocking effects, multistage cube network, nonuniform traffic patterns, switch box implementation
3	Jaehong Shim, Kyongok Yun, Kyunghee Choi, Gihyun Jung, Seungkyu Park, Dugkyoo Choi	A switch scheduling algorithm for periodic messages using laxity decomposition method.	RTCSA	1997	DBLP DOI BibTeX RDF	switch scheduling algorithm, periodic messages, laxity decomposition method, real time messages scheduling, laxities, schedulable messages, MLF algorithm, time division multiple access, simulation results, traffic matrix
3	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
3	Joseph Kee-Yin Ng, Shibin Song, Wei Zhao	Integrated delay analysis of regulated ATM switch. (PDF / PS)	IEEE Real-Time Systems Symposium	1997	DBLP DOI BibTeX RDF	integrated delay analysis, regulated ATM switch, worst case delay, hard real-time connection, real-time connection traffic, arrival functions, priority driven scheduling, FIFO scheduling, admission probability, cell delay estimation, performance, asynchronous transfer mode, deadline, simulation experiments, service functions, piecewise linear functions
3	Kuo-Pao Fan, Chung-Ta King	Optimal Software Multicast on Wormhole Switch-based Networks.	ISPAN	1997	DBLP DOI BibTeX RDF	multicast, wormhole routing, switch, irregular network