Search results for "switching activity"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Bounds on FSM Switching Activity.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Low power design, Markov models, Hamming distance, State assignment, Switching activity
3	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
3	Felipe Machado, Teresa Riesgo, Yago Torroja	Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.	PATMOS	2008	DBLP DOI BibTeX RDF	activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design
3	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Scan-Based Tests with Low Switching Activity.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test
3	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
3	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
3	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	test vector ordering, test, low power, switching activity
3	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
3	Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto	Switching activity analysis using Boolean approximation method.	ICCAD	1995	DBLP DOI BibTeX RDF	Signal Correlation, Power Estimation, Switching Activity, Signal Probability
2	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Switching activity estimation for shift-and-add based constant multipliers.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Shu-Cheng Chou, Mong-Kai Ku, Chia-Yu Lin	Switching activity reducing layered decoding algorithm for LDPC codes.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Rizwan Mudassir, Mohab Anis, Javid Jaffari	Switching activity reduction in low power Booth multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Oscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg	Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data.	PATMOS	2007	DBLP DOI BibTeX RDF	dual bit type, coefficient reordering, MAC, FIR filter, switching activity
2	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
2	Wang-Dauh Tseng	Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	transition density, switching activity during test, clique, low power testing, full scan
2	Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
2	Seongmoon Wang, Sandeep K. Gupta	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the Data Switching Activity on Serial Link Buses.	ISQED	2006	DBLP DOI BibTeX RDF
2	Felipe Machado, Teresa Riesgo, Yago Torroja	A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang	Switching-activity driven gate sizing and Vth assignment for low power design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Snehashis Roy, Sukumar Jairam, H. Udayakumar	A Methodology for Switching Activity Based IO Powerpad Optimisation.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the data switching activity of serialized datastreams.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
2	Siobhán Launders, Colin Doyle, Wesley Cooper	Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan	Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign bit reduction encoding for low power applications.	DAC	2005	DBLP DOI BibTeX RDF	signed multiplier, sing extension, low power, switching activity, bus encoding
2	Sanjukta Bhanja, N. Ranganathan	Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Shu-Shin Chin, Sangjin Hong, Suhwan Kim	Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.	ISVLSI	2004	DBLP DOI BibTeX RDF
2	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
2	Sanjukta Bhanja, N. Ranganathan	Switching activity estimation of VLSI circuits using Bayesian networks.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner	Switching Activity Estimation in Non-linear Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Jason Helge Anderson, Farid N. Najm	Switching activity analysis and pre-layout activity prediction for FPGAs.	SLIP	2003	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, power, estimation
2	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Upper and lower bounds on FSM switching activity.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Masayuki Ito, David G. Chinnery, Kurt Keutzer	Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition.	ICCD	2003	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Sandeep K. Gupta	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Seongmoon Wang, Sandeep K. Gupta	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	C. Baena, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos J. Jiménez, Manuel Valencia	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	A Real Delay Switching Activity Simulator Based on Petri Net Modeling.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Sanjukta Bhanja, N. Ranganathan	Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler	Switching activity estimation of finite state machines for low power synthesis.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Sanjukta Bhanja, N. Ranganathan	Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.	ICCD	2002	DBLP DOI BibTeX RDF
2	Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj	Estimation of state line statistics in sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	signal statistics, transition density, finite-state machine, sequential circuit, Power estimation, switching activity, signal probability
2	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Switching activity generation with automated BIST synthesis forperformance testing of interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
2	Diana Marculescu, Radu Marculescu, Massoud Pedram	Theoretical bounds for switching activity analysis in finite-state machines.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical analysis of word-level switching activity in the presence of glitching and correlation.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba	Static Compaction Techniques to Control Scan Vector Power Dissipation.	VTS	2000	DBLP DOI BibTeX RDF	Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing
2	Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan	Computation of lower bounds for switching activity using decision theory.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
2	Janardhan H. Satyanarayana, Keshab K. Parhi	Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger	Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach.	DATE	1999	DBLP DOI BibTeX RDF
2	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Radu Marculescu, Diana Marculescu, Massoud Pedram	Probabilistic modeling of dependencies during switching activity analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Diana Marculescu, Radu Marculescu, Massoud Pedram	Theoretical bounds for switching activity analysis in finite-state machines.	ISLPED	1998	DBLP DOI BibTeX RDF
2	Vamsi Krishna, N. Ranganathan	A Methodology for High Level Power Estimation and Exploration.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low Power Designs, Power Estimation, Switching Activity, High Level Designs
2	José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White	Estimation of average switching activity in combinational logic circuits using symbolic simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
2	Salvador Manich, Joan Figueras	Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy	A low power based system partitioning and binding technique for multi-chip module architectures.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
2	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
2	Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang	Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	maximum switching activity, uncertainty waveforms, circuit reliability
2	José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
2	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
1	Hassan Salmani, Mohammad Tehranipoor	Layout-Aware Switching Activity Localization to Enhance Hardware Trojan Detection.	IEEE Transactions on Information Forensics and Security	2012	DBLP DOI BibTeX RDF
1	Brendan Crowley, Vincent Gaudet	Switching Activity Minimization in Iterative LDPC Decoders.	Signal Processing Systems	2012	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Reducing the switching activity of test sequences under transparent-scan.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Elie Elaaraj, Iyad Ouaiss	A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity.	PRDC	2011	DBLP DOI BibTeX RDF
1	Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu	Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Wen Bin Ye, Ya Jun Yu	Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test Sequences with Reduced and Increased Switching Activity.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Xin Man, Takashi Horiyama, Shinji Kimura	Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Switching Activity as a Test Compaction Heuristic for Transition Faults.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Zulhakimi Razak, Ahmet T. Erdogan, Tughrul Arslan	Low power noise detection circuit utilizing switching activity measurement method.	DASIP	2010	DBLP DOI BibTeX RDF
1	Vincent C. Gaudet, Warren J. Gross	Switching Activity in Stochastic Decoders.	ISMVL	2010	DBLP DOI BibTeX RDF	stochastic decoding, low-power design, iterative decoding, LDPC
1	Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng	Improved weight assignment for logic switching activity during at-speed test pattern generation.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab	At-speed scan test with low switching activity.	VTS	2010	DBLP DOI BibTeX RDF
1	Fahad Qureshi, Oscar Gustafsson	Twiddle factor memory switching activity analysis of radix-22 and equivalent FFT algorithms.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
1	Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas	Gating internal nodes to reduce power during scan shift.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	gating internal nodes, scan shift power reduction, low power test
1	Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu	Logic synthesis for low power using clock gating and rewiring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, logic synthesis, clock gating
1	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara	Graph theoretic approach for scan cell reordering to minimize peak shift power.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power droop, scan chain reordering, peak power
1	Prassanna Sithambaram, Alberto Macii, Enrico Macii	Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Lei Chen, Shinji Kimura	Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity.	IEICE Transactions	2009	DBLP BibTeX RDF
1	María C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio, Jose Manuel Mendias	Subword Switching Activity Minimization to Optimize Dynamic Power Consumption.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.	PRDC	2009	DBLP DOI BibTeX RDF
1	Tom English, Ka Lok Man, Emanuel M. Popovici	BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, M. Aso, Hiroshi Furukawa	CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau	Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Kenny Johansson, Oscar Gustafsson, Linda DeBrunner	Estimation of the Switching Activity in Shift-and-add based Computations.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Madhu Mutyam	Selective shielding technique to eliminate crosstalk transitions.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	power consumption, Crosstalk, switching activity, bus encoding
1	Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco	Event-driven gate-level simulation with GP-GPUs.	DAC	2009	DBLP DOI BibTeX RDF	gate-level simulation, general purpose graphics processing unit (GP-GPU), high-performance simulation
1	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
1	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	Efficient partial scan cell gating for low-power scan-based testing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan-based testing
1	Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	Defect Aware to Power Conscious Tests - The New DFT Landscape.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Meikang Qiu, Meiqin Liu, Hao Li, Hung-Chung Huang, Wenyuan Li, Jiande Wu	Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Optimization, Real-time, Multi-core, Assignment, Loop scheduling
1	Jeremy Lee, Mohammad Tehranipoor	Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF