Search results for "synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
7	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
6	Sylvain Lefebvre, Hugues Hoppe	Appearance-space texture synthesis.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	RTT synthesis, anisometric synthesis, exemplar-based synthesis, feature-based synthesis, dimensionality reduction, surface textures
6	J. Williams, Mark J. Clement	Distributed Polyphonic Music Synthesis. (PDF / PS)	HPDC	1997	DBLP DOI BibTeX RDF	polyphonic music synthesis, music synthesis, distributed music synthesis, Csound music synthesis package, multiple servers, networks, music, communication protocols, distributed multimedia
6	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
6	H. Fatih Ugurdag, Thomas E. Fuhrman	Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
6	Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya	Synthesis of system-level communication by an allocation-based approach.	ISSS	1995	DBLP DOI BibTeX RDF	allocation-based approach, high level primitives, interconnected processes, protocol selection, system-level communication synthesis, protocols, high level synthesis, systems analysis, cost function, interface synthesis, communication control
6	Frank Vahid	Procedure exlining: a transformation for improved system and behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
6	Herman Schmit, Donald E. Thomas	Array mapping in behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	array grouping, array mapping, memory components, memory design space, schedule length, scheduling, data structures, memory architecture, hardware description languages, binding, behavioral synthesis, access times, design representation, hardware synthesis, synthesis tool
6	Miodrag Potkonjak, Wayne Wolf	Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.	ICCAD	1995	DBLP DOI BibTeX RDF	allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
5	Greg Stitt, Frank Vahid	Thread warping: a framework for dynamic synthesis of thread accelerators.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	dynamic synthesis, thread warping, warp processing, FPGA, synthesis, multi-core, threads, just-in-time compilation
5	Eike Grimpe, Frank Oppenheimer	Extending the SystemC synthesis subset by object-oriented features.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	C/C++ based design, object-orientation, high-level synthesis, SystemC, system level design, hardware description language, hardware synthesis
5	Mukund Sivaraman, Shail Aditya	Cycle-time aware architecture synthesis of custom hardware accelerators.	CASES	2002	DBLP DOI BibTeX RDF	embedded hardware architecture synthesis, operator chaining, target clock period, timing during scheduling, high-level synthesis, timing analysis, delay analysis, clock frequency
5	Ingo Sander, Axel Jantsch, Zhonghai Lu	A Case Study of Hardware and Software Synthesis in ForSyDe.	ISSS	2002	DBLP DOI BibTeX RDF	system design, design methodology, software synthesis, hardware synthesis
5	Andreas Hamfelt, Jørgen Fischer Nilsson	Inductive Synthesis of Logic Programs by Composition of Combinatory Program Schemes.	LOPSTR	1998	DBLP DOI BibTeX RDF	logic program schemata, logical combinators, synthesis by composition and specialization of schemas, inductive synthesis, metalogic program environment
5	Mihhail Matskin, Enn Tyugu	Strategies of Structural Synthesis of Programs. (PDF / PS)	ASE	1997	DBLP DOI BibTeX RDF	structural program synthesis strategies, deductive program synthesis method, compositional programming, decidable logical calculus, PSPACE complexity, independent subtasks, iteration synthesis, regular data structures, heuristics, programming environments, structured programming, proof search, search efficiency
5	Alessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto	The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF	virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling
5	Alex Orailoglu	Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
5	Miodrag Potkonjak, Anantha Chandrakasan	Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
5	Mahsa Vahidi, Alex Orailoglu	Testability metrics for synthesis of self-testable designs and effective test plans.	VTS	1995	DBLP DOI BibTeX RDF	testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
5	Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
5	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
5	Jan Madsen, Bjarne Hald	An approach to interface synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	channel optimization, client-side interface description, client/server module synthesis, communication events formalization, existing module reuse, multiple client/server environment, one-sided interface description, server interface description, software reusability, application program interfaces, client-server systems, subroutines, interface synthesis, point-to-point communication
5	Ahmad Abualsamid, Raed Alqadi, Parameswaran Ramanathan	Distributed synthesis of real-time computer systems. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	engineering workstations, distributed synthesis, design library, processor estimation, application constraints, suitable architecture identification, application task scheduling, runtime speedup, scheduling, real-time systems, computational complexity, parallelization, CAD, distributed processing, high level synthesis, high-level synthesis, software libraries, workstation network, real-time computer systems, resource estimation, component library
5	Ti-Yen Yen, Wayne Wolf	Communication synthesis for distributed embedded systems.	ICCAD	1995	DBLP DOI BibTeX RDF	analysis algorithm, real-time systems, embedded systems, CAD, distributed processing, distributed embedded systems, interprocess communication, delay bounds, system buses, communication links, co-synthesis, synthesis algorithm, hardware-software co-synthesis
5	Balakrishnan Iyer, Ramesh Karri, Israel Koren	Phantom redundancy: a high-level synthesis approach for manufacturability.	ICCAD	1995	DBLP DOI BibTeX RDF	fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
5	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
5	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
5	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
5	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
4	Sumit Gulwani	Dimensions in program synthesis.	PPDP	2010	DBLP DOI BibTeX RDF	deductive synthesis, inductive synthesis, sat solving, smt solving, machine learning, genetic programming, programming by demonstration, belief propagation, programming by examples, probabilistic inference
4	Hideyuki Mizuno, Satoshi Takahashi	Unit selection using k-nearest neighbor search for concatenative speech synthesis.	IUCS	2009	DBLP DOI BibTeX RDF	concatenative speech synthesis, synthesis unit selection, nearest neighbor search, text to speech
4	Motonori Doi, Rie Ohtsuki, Rie Hikima, Osamu Tanno, Shoji Tominaga	Synthesis of Facial Images with Foundation Make-Up.	CCIW	2009	DBLP DOI BibTeX RDF	Facial image synthesis, Make-up foundation, Kubelka-Munk theory, Texture synthesis, Color image, Multi-resolution analysis
4	Xijin Tang	Qualitative Meta-synthesis Techniques for Analysis of Public Opinions for in-depth Study.	Complex	2009	DBLP DOI BibTeX RDF	qualitative meta-synthesis, CorMap, iView, meta-synthesis, word association
4	Thomas Hurtut, Pierre-Edouard Landes, Joëlle Thollot, Yann Gousseau, R. Drouillhet, J.-F. Coeurjolly	Appearance-guided synthesis of element arrangements by example.	NPAR	2009	DBLP DOI BibTeX RDF	by-example synthesis, vector texture synthesis, NPR
4	Jason Cong, Albert Liu, Bin Liu 0006	A variation-tolerant scheduler for better than worst-case behavioral synthesis.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, variation, behavioral synthesis
4	Nicolas Bonneel, George Drettakis, Nicolas Tsingos, Isabelle Viaud-Delmon, Doug L. James	Fast modal sounds with scalable frequency-domain synthesis.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	modal synthesis, real-time audio rendering, physically based animation, sound synthesis
4	Dominik Bauer, Jim Kannampuzha, Bernd J. Kröger	Articulatory Speech Re-synthesis: Profiting from Natural Acoustic Speech Data.	COST 2102 Conference (Prague)	2008	DBLP DOI BibTeX RDF	articulatory speech synthesis, vocal tract action units, speech, articulation, re-synthesis
4	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
4	Paul Tarau, Brenda Luderman	Revisiting exact combinational circuit synthesis.	SAC	2008	DBLP DOI BibTeX RDF	exact combinational circuit synthesis, logic programming and circuit design, minimal transistor-count circuit synthesis
4	Sotiris Karabetsos, Pirros Tsiakoulis, Aimilios Chalamandaris, Spyros Raptis	HMM-Based Speech Synthesis for the Greek Language.	TSD	2008	DBLP DOI BibTeX RDF	Greek Language, Statistical Parametric Speech Synthesis, HMM, Hidden Markov Model, Speech Synthesis, Text to Speech
4	Frank Vahid, Tony Givargis	Highly-cited ideas in system codesign and synthesis.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	hardware/software codesign, citations, system synthesis
4	Felix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich	Symbolic voter placement for dependability-aware system synthesis.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	mttuf, bdd, system synthesis, voter, mean time to failure, mttf
4	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
4	Greg Stitt, Frank Vahid	Binary synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Binary synthesis, synthesis from software binaries, FPGA, hardware/software codesign, hardware/software partitioning, configurable logic, warp processors
4	Ganesh Ramanarayanan, Kavita Bala	Constrained Texture Synthesis via Energy Minimization.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	detail synthesis, image analogies, Texture synthesis, super-resolution
4	Howard Zhou, Jie Sun 0004, Greg Turk, James M. Rehg	Terrain Synthesis from Digital Elevation Models.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	Terrain synthesis, terrain analysis, texture synthesis, Digital Elevation Models
4	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
4	Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley	Performance-driven syntax-directed synthesis of asynchronous processors.	CASES	2007	DBLP DOI BibTeX RDF	handshake components, syntax-directed synthesis, asynchronous circuits
4	Borzoo Bonakdarpour, Sandeep S. Kulkarni, Fuad Abujarad	Distributed Synthesis of Fault-Tolerant Programs in the High Atomicity Model.	SSS	2007	DBLP DOI BibTeX RDF	Parallel synthesis, Fault-tolerance, Distributed algorithms, Program transformation, Program synthesis
4	Hansu Cho, Samar Abdi, Daniel Gajski	Interface synthesis for heterogeneous multi-core systems from transaction level models.	LCTES	2007	DBLP DOI BibTeX RDF	HW-SW co-design, universal bridge, channel, transaction level model, communication synthesis, interface synthesis
4	Brett H. Meyer, Donald E. Thomas	Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	bus architecture synthesis, embedded multiprocessor systems-on-chip, partitioning, sharing, memory allocation, data mapping
4	Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang	Reliable multiprocessor system-on-chip synthesis.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	synthesis, multiprocessor system-on-chip, thermal
4	Andrew Ireland, Jamie Stark	Combining Proof Plans with Partial Order Planning for Imperative Program Synthesis.	Autom. Softw. Eng.	2006	DBLP DOI BibTeX RDF	partial order planning, deductive synthesis, program synthesis, proof planning
4	Zhigang Deng, Ulrich Neumann, John P. Lewis, Tae-Yong Kim 0002, Murtaza Bulut, Shrikanth Narayanan	Expressive Facial Animation Synthesis by Learning Speech Coarticulation and Expression Spaces.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	expressive speech, animation synthesis, speech coarticulation, motion capture, texture synthesis, Facial animation, data-driven
4	Jian Liu, Jicheng Fu, Yansheng Zhang, Farokh B. Bastani, I-Ling Yen, Ann T. Tai, Savio N. Chau	Deductive Glue Code Synthesis for Embedded Software Systems Based on Code Patterns.	ISORC	2006	DBLP DOI BibTeX RDF	Automated code synthesis, Deductive code synthesis, Real-time system, Code patterns
4	Rupal Patel, Michael Everett, Eldar Sadikov	Loudmouth: : modifying text-to-speech synthesis in noise.	ASSETS	2006	DBLP DOI BibTeX RDF	text-to-speech synthesis (TTS), speech synthesis, augmentative and alternative communication (AAC)
4	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
4	Ilya Issenin, Nikil Dutt	Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	customized memory hierarchy, hierarchical TDMA buses, data reuse, multiprocessor system-on-chip, communication synthesis
4	Manjunath Kudlur, Kevin Fan, Scott A. Mahlke	Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system-level synthesis, loop accelerator, application-specific hardware
4	Sylvain Lefebvre, Hugues Hoppe	Parallel controllable texture synthesis.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	Gaussian stack, coordinate jitter, data amplification, neighborhood matching, runtime content synthesis, synthesis magnification
4	Hyunok Oh, Nikil D. Dutt, Soonhoi Ha	Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	automatic code synthesis, modulo buffering, shift buffering, buffer management, synchronous dataflow
4	Vinu Vijay Kumar, John Lach	Highly flexible multi-mode system synthesis.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	multi-mode synthesis, reconfigurability, adaptable systems
4	Oliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn	Conflict analysis in multiprocess synthesis for optimized system integration.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	scheduling, systems-on-chip, system level design, concurrent systems, binding, behavioral synthesis
4	Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	virtual machine, synthesis, accelerator
4	Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell	High-level synthesis for large bit-width multipliers on FPGAs: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
4	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard	SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	high-level synthesis, memory synthesis
4	Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton	A General Purpose Behavioural Asynchronous Synthesis System.	ASYNC	2004	DBLP DOI BibTeX RDF	Behavioural synthesis, asynchronous synthesis, cryptography
4	Sandeep S. Kulkarni, Borzoo Bonakdarpour, Ali Ebnenasir	Mechanical Verification of Automatic Synthesis of Fault-Tolerant Programs.	LOPSTR	2004	DBLP DOI BibTeX RDF	Addition of faulttolerance, Fault-tolerance, Program transformation, Theorem proving, Program synthesis, PVS, Mechanical verification
4	Hyunuk Jung, Soonhoi Ha	Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign
4	Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin	Memory accesses management during high level synthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis
4	Hirozumi Yamaguchi, Khaled El-Fakih, Gregor von Bochmann, Teruo Higashino	Protocol synthesis and re-synthesis with optimal allocation of resources based on extended Petri nets.	Distributed Computing	2003	DBLP DOI BibTeX RDF	Protocol re-synthesis, Distributed system, Petri net, Service specification, Protocol specification, Protocol synthesis
4	Byoungro So, Pedro C. Diniz, Mary W. Hall	Using estimates from behavioral synthesis tools in compiler-directed design space exploration.	DAC	2003	DBLP DOI BibTeX RDF	synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
4	Francis Alexandre, Khaled Bsaïes, Moussa Demba	Predicate Synthesis from Inductive Proof Attempt of Faulty Conjectures.	LOPSTR	2003	DBLP DOI BibTeX RDF	Corrective predicate, implicative formulas, folding/unfolding rules, theorem proving, program synthesis, abduction
4	Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy	An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications
4	Amol Bakshi, Jingzhao Ou, Viktor K. Prasanna	Towards automatic synthesis of a class of application-specific sensor networks.	CASES	2002	DBLP DOI BibTeX RDF	sensor networks, energy efficiency, design environments, automatic synthesis
4	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
4	Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn	Controller Estimation for FPGA Target Architectures during High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	FPGA, controller, high-level synthesis, area estimation
4	Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta	Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.	ISSS	2002	DBLP DOI BibTeX RDF	common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis
4	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
4	Ali Dasdan	Efficient algorithms for debugging timing constraint violations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
4	Pao-Ann Hsiung	POSE: a parallel object-oriented synthesis environment.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	design-completion check, synthesis rollback, object-oriented technology, hardware synthesis, parallel design
4	Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara	Strong self-testability for data paths high-level synthesis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
4	Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken	Manufacturability and Testability Oriented Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
4	Chittaranjan A. Mandal, R. M. Zimmer	A Genetic Algorithm for the Synthesis of Structured Data Paths.	VLSI Design	2000	DBLP DOI BibTeX RDF	Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation
4	Heinz Mayer	Image-Based Texture Analysis for Realistic Image Synthesis.	SIBGRAPI	2000	DBLP DOI BibTeX RDF	image based texture analysis, digital image synthesis, intensity values, highlighting artifacts, image based measurement system, BRDF values, diffuse reflectance coefficient, compact description, measured surface properties, arbitrary shape, standard CCD camera, image texture, reflectance model, realistic image synthesis, light source, measurement system, surface reflectance, bidirectional reflectance distribution function
4	Minjie Zhang, Chengqi Zhang	Potential Cases, Methodologies, and Strategies of Synthesis of Solutions in Distributed Expert Systems.	IEEE Trans. Knowl. Data Eng.	1999	DBLP DOI BibTeX RDF	Distributed expert systems, synthesis of solutions, synthesis strategies, inductive methods, methodologies, analysis methods
4	Harry Hengster, Bernd Becker	Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability.	FTCS	1999	DBLP DOI BibTeX RDF	EXOR-based Synthesis, Decision Diagrams, Synthesis for Testability, High Speed Circuits
4	Pradeep Prabhakaran, Prithviraj Banerjee	Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis.	VLSI Design	1998	DBLP DOI BibTeX RDF	timing driven synthesis, High-level synthesis, floorplanning
4	Bharat P. Dave, Niraj K. Jha	COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures.	VLSI Design	1998	DBLP DOI BibTeX RDF	scheduling, distributed systems, embedded systems, hierarchy, allocation, system synthesis, hardware-software co-synthesis
4	José M. Mendías, Román Hermida	Correct High-Level Synthesis: a Formal Perspective.	DATE	1998	DBLP DOI BibTeX RDF	automatic formal synthesis, formal verification, high-level synthesis, streams
4	Oliver Bringmann, Wolfgang Rosenstiel	Cross-Level Hierarchical High-Level Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	Hierarchical Synthesis, Complex Components, High-Level Synthesis
4	Bharat P. Dave, Niraj K. Jha	CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures.	DATE	1998	DBLP DOI BibTeX RDF	aperiodic task graphs, scheduling, distributed systems, embedded systems, allocation, system synthesis, hardware-software co-synthesis
4	Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel	Verification by Simulation Comparison using Interface Synthesis.	DATE	1998	DBLP DOI BibTeX RDF	Simulation Comparison, Verification, High-Level Synthesis, Interface Synthesis
4	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
4	Jon Christensen, Joe Marks, J. Thomas Ngo	Automatic motion synthesis for 3D mass-spring models.	The Visual Computer	1997	DBLP DOI BibTeX RDF	Animation, Stochastic optimization, Motion synthesis, Heuristic methods, Mass-spring models, Controller synthesis
4	Pierre Flener, Kung-Kiu Lau, Mario Ornaghi	Correct-Schema-Guided Synthesis of Steadfast Programs. (PDF / PS)	ASE	1997	DBLP DOI BibTeX RDF	steadfast programs, semi-automated software development, schema correctness, structured program design principles, hierarchical program synthesis, syntactic representation, higher-order expressions, informal knowledge capture, program schema formalisation, open first-order logical theory, open logic program, logic programming, program synthesis, domain knowledge
4	Sumit Roy, Prithviraj Banerjee	A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy
4	Mostafa H. Abd-El-Barr, M. N. Hasan, G. A. Hamid	On the Synthesis of MVL Functions Using Input and Output Phase Assignments. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic
4	Katsuyuki Kamei, Minoru Maruyama, Kazuo Seo	Scene Synthesis by Assembling Striped Areas of Source Images. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	striped areas assembling, source images, image-based rendering method, scene synthesis, memory data management, walkthrough operations, flythrough system, real time, virtual environment, image synthesis, rendering (computer graphics), view synthesis