Search results for "synthesis procedure"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Alex Orailoglu	Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
2	S. C. Chan, Andrew K. C. Wong	Synthesis and Recognition of Sequences.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	sequences synthesis, sequences recognition, hierarchical sequence synthesis procedure, taxonomic hierarchy, unsupervised classification procedure, pattern recognition, probability, alignment, supervised classification, alphabet
1	Ruxandra L. Costea, Corneliu A. Marinov	Recurrent neural network as a KWTA selector: A synthesis procedure.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Viktor Kuncak, Mikaël Mayer, Ruzica Piskac, Philippe Suter	Complete functional synthesis.	PLDI	2010	DBLP DOI BibTeX RDF	bapa, synthesis procedure, decision procedure, presburger arithmetic
1	George Christelis, Michael Rovatsos	Automated norm synthesis in an agent-based planning environment.	AAMAS	2009	DBLP DOI BibTeX RDF	social laws, coordination, conflict resolution, norms, automated planning
1	Silvia Ferrari	Multiobjective Algebraic Synthesis of Neural Control Systems by Implicit Model Following.	IEEE Transactions on Neural Networks	2009	DBLP DOI BibTeX RDF
1	Armando Solar-Lezama	The Sketching Approach to Program Synthesis.	APLAS	2009	DBLP DOI BibTeX RDF
1	Luís Mendes, Eduardo José Solteiro Pires, Paulo B. de Moura Oliveira, José António Tenreiro Machado, Nuno M. Fonseca Ferreira, João Caldinhas Vaz, Maria J. Rosário	Design Optimization of Radio Frequency Discrete Tuning Varactors.	EvoWorkshops	2009	DBLP DOI BibTeX RDF	automated circuit synthesis, radio frequency integrated circuits, Evolutionary algorithms, analog circuit design
1	Eduardo José Solteiro Pires, Luís Mendes, Paulo B. de Moura Oliveira, José António Tenreiro Machado, João Caldinhas Vaz, Maria J. Rosário	Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm.	IWANN	2009	DBLP DOI BibTeX RDF	automated circuit synthesis and radio-frequency integrated circuits, Particle swarm optimization, analog circuit design
1	Almitra Pradhan, Ranga Vemuri	A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout-aware, matrix-models, sizing
1	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Tao Xu, Krishnendu Chakrabarty	Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.	JETC	2008	DBLP DOI BibTeX RDF	Physical design automation, microfluidics, biochips, module placement
1	Spring Berman, Ádám M. Halász, M. Ani Hsieh, Vijay Kumar	Navigation-based optimization of stochastic strategies for allocating a robot swarm among multiple sites.	CDC	2008	DBLP DOI BibTeX RDF
1	Hakan Köroglu, Carsten W. Scherer	Robust generalized asymptotic regulation against non-stationary sinusoidal disturbances.	CDC	2008	DBLP DOI BibTeX RDF
1	I-Hung Khoo, Hari C. Reddy, George S. Moschytz	Delta discrete-time operator based realization procedure for low sensitivity sampled-data and digital ladder filters.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Riccardo Rovatti, Gianluca Mazzini, Gianluca Setti, Stefano Vitali	Linear probability feedback processes.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Gülin Tulunay, Sina Balkir	Synthesis of RF CMOS Low Noise Amplifiers.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Gülin Tulunay, Sina Balkir	A Synthesis Tool for CMOS RF Low-Noise Amplifiers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Philippe Darondeau	On the Synthesis of Zero-Safe Nets.	Concurrency, Graphs and Models	2008	DBLP DOI BibTeX RDF
1	S. A. Kanellopoulos, G. Fikioris, Athanasios D. Panagopoulos, John D. Kanellopoulos	A modified synthesis procedure for first order stochastic differential equations for the simulation of baseband random processes.	Signal Processing	2007	DBLP DOI BibTeX RDF
1	Leslie Ikemoto, Okan Arikan, David A. Forsyth	Quick transitions with cached multi-way blends.	SI3D	2007	DBLP DOI BibTeX RDF	motion evaluation, motion synthesis, motion blending
1	Amab Sinha, Sumana Gupta	Approximation of Conditional Density of Markov Random Field and its Application to Texture Synthesis.	ICIP	2007	DBLP DOI BibTeX RDF
1	Spring Berman, Ádám M. Halász, Vijay Kumar, Stephen Pratt	Bio-Inspired Group Behaviors for the Deployment of a Swarm of Robots to Multiple Destinations.	ICRA	2007	DBLP DOI BibTeX RDF
1	Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch	Optimal Synthesis of MITE Translinear Loops.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.	VTS	2007	DBLP DOI BibTeX RDF
1	Xindi Cai, Danil V. Prokhorov, Donald C. Wunsch II	Training Winner-Take-All Simultaneous Recurrent Neural Networks.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	A. Sanchez, J. G. Douriet, E. Ramirez	Synthesis of a Class of Discrete-Event Controllers for Large Manufacturing Systems.	IEEE Transactions on Systems, Man, and Cybernetics, Part C	2007	DBLP DOI BibTeX RDF
1	Orcun Goksel, Septimiu E. Salcudean	Real-Time Synthesis of Image Slices in Deformed Tissue from Nominal Volume Images.	MICCAI	2007	DBLP DOI BibTeX RDF
1	Avijit Dutta, Nur A. Touba	Synthesis of Efficient Linear Test Pattern Generators.	DFT	2006	DBLP DOI BibTeX RDF
1	J. C. Hwang, C. W. Huang, C. T. Cheng	The Development of Load Characteristics Information Network System to Improve the Estimated Efficiency of Load Synthesis in Taipower.	ICICIC	2006	DBLP DOI BibTeX RDF	load survey, load synthesis, network database, customer management
1	Qi Zhu, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli	A semantic-driven synthesis flow for platform-based design.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function
1	Michal Aharon, Ron Kimmel	Representation Analysis and Synthesis of Lip Images Using Dimensionality Reduction.	International Journal of Computer Vision	2006	DBLP DOI BibTeX RDF	automatic lipreading, multidimensional scaling, dimension reduction, speech synthesis, locally linear embedding, image sequence processing
1	Spyros Tragoudas, Vijay Nagarandal	On-chip embedding mechanisms for large sets of vectors for delay test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	M. Panella, A. S. Gallo	An input-output clustering approach to the synthesis of ANFIS networks.	IEEE T. Fuzzy Systems	2005	DBLP DOI BibTeX RDF
1	Christophe Damas, Bernard Lambeau, Pierre Dupont, Axel van Lamsweerde	Generating Annotated Behavior Models from End-User Scenarios.	IEEE Trans. Software Eng.	2005	DBLP DOI BibTeX RDF	Scenario-based elicitation, synthesis of behavior models, incremental learning, labeled transition systems, model validation, message sequence charts, analysis tools, scenario generation, invariant generation
1	Irith Pomeranz, Sudhakar M. Reddy	Autoscan: a scan design without external scan inputs or outputs.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Kihong Kim, Jinkeun Hong, Jongin Lim	Analysis/Synthesis of Speech Signals Based on AbS/OLA Sinusoidal Modeling Using Elliptic Filter.	IDEAL	2005	DBLP DOI BibTeX RDF
1	Yu-Len Huang	Wavelet-based image interpolation using multilayer perceptrons.	Neural Computing and Applications	2005	DBLP DOI BibTeX RDF	Image resampling, Subband filtering, Neural network, Wavelet transform, Interpolation
1	Michael Vollmer	An approach to automatic generation of wave digital structures from PDEs.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers	Efficient Pattern Mapping for Deterministic Logic BIST.	ITC	2004	DBLP DOI BibTeX RDF	BDDs, Logic BIST
1	Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy	Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	output response compression, Built-in self-test, scan design
1	Andrea Balluchi, Federico Di Natale, Alberto L. Sangiovanni-Vincentelli, Jan H. van Schuppen	Synthesis for Idle Speed Control of an Automotive Engine.	HSCC	2004	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Jiuchao Feng, C. K. Tse, Yuhui Qiu	Wavelet-transform-based strategy for generating new Chinese fonts.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Baskar Sridharan, Aditya P. Mathur, Kai-Yuan Cai	Using Supervisory Control to Synthesize Safety Controllers for Connected Spaces.	QSIC	2003	DBLP DOI BibTeX RDF
1	Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh	Synthesis Of Programmable Current Mode Linear Analog Circuit.	VLSI Design	2003	DBLP DOI BibTeX RDF	Band Reject Filter, Low Pass Filter, Band Pass Filter, Operational Transconductance Amplifier, High Pass Filter
1	Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams	A Reconfigurable Shared Scan-in Architecture.	VTS	2003	DBLP DOI BibTeX RDF
1	Richard St.-Denis	Designing reactive systems: integration of abstraction techniques into a synthesis procedure.	Journal of Systems and Software	2002	DBLP DOI BibTeX RDF
1	Massimiliano Chiodo	Optimization and synthesis for complex reactive embedded systems by incremental collapsing.	CODES	2002	DBLP DOI BibTeX RDF	real-time systems, embedded systems, finite-state machines, software synthesis
1	Min Zhao, Sachin S. Sapatnekar	Technology mapping algorithms for domino logic.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	XOR/XNOR logic, dual-monotonic gates, parameterized library, phase assignment, synthesis, technology mapping, Domino logic
1	Gurdip Singh, Bob S. Maddula, Qiang Zeng	Enhancing Real-Time Event Service for Synchronization in Object-Oriented Distributed Systems. (PDF / PS)	Symposium on Object-Oriented Real-Time Distributed Computing	2002	DBLP DOI BibTeX RDF
1	Sung Tae Jung, Chris J. Myers	Direct synthesis of timed circuits from free-choice STGs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Andrea Balluchi, Luca Benvenuti, Maria Domenica Di Benedetto, Alberto L. Sangiovanni-Vincentelli	Design of Observers for Hybrid Systems.	HSCC	2002	DBLP DOI BibTeX RDF
1	J. Park, H.-Y. Kim, Y. Park, S.-W. Lee	A synthesis procedure for associative memories based on space-varying cellular neural networks.	Neural Networks	2001	DBLP DOI BibTeX RDF
1	Igor M. Filanovsky, P. N. Matkhanov	On synthesis of a reactance network having the step response described by a sinusoid with a given envelope.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Igor M. Filanovsky, P. N. Matkhanov	On synthesis of a network to have the impulse response described by an integer power of sinusoid over its semi-period.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Stream synthesis for efficient power simulation based on spectral transforms.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Marc Frappier, Richard St.-Denis	Towards a Computer-Aided Design of Reactive Systems.	EUROCAST	2001	DBLP DOI BibTeX RDF
1	Vladimir N. Shashikhin	Robust Control Using Interval Analysis.	Reliable Computing	2001	DBLP DOI BibTeX RDF
1	Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power synthesis of sum-of-products computation (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
1	Sung Tae Jung, Chris J. Myers	Direct synthesis of timed asynchronous circuits.	ICCAD	1999	DBLP BibTeX RDF
1	Felice Balarin, Massimiliano Chiodo	Software Synthesis for Complex Reactive Embedded Systems.	ICCD	1999	DBLP DOI BibTeX RDF
1	Bradley A. Minch	Synthesis of multiple-input translinear element log-domain filters.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Robert Thacker, Wendy Belluomini, Chris J. Myers	Timed Circuit Synthesis Using Implicit Methods.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	POSET timing and its application to the synthesis and verification of gate-level timed circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	RP-SYN: synthesis of random pattern testable circuits with test point insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	A Synthesis Procedure for Flexible Logic Functions.	DATE	1998	DBLP DOI BibTeX RDF	comparison units, flexible functions, logic synthesis
1	Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino	Timed Supersetting and the Synthesis of Telescopic Units.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Pipelined Design, Logic Synthesis, Timing Analysis
1	Wendy Belluomini, Chris J. Myers	Efficient Timing Analysis Algorithms for Timed State Space Exploration.	ASYNC	1997	DBLP DOI BibTeX RDF	timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders
1	Xiaoming Yu, Yinghua Min	Design of delay-verifiable combinational logic by adding extra inputs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	delay-verifiable combinational logic, delay testability, synthesis, combinational circuits, hardware overhead, temporal behavior
1	Christian Dufaza, Yervant Zorian	On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Andre Hertwig, Hans-Joachim Wunderlich	Fast controllers for data dominated applications.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Takami Satonaka, Takaaki Baba, Tatsuo Otsuki, Takao Chikamura, Teresa H. Y. Meng	Object Recognition with Luminance, Rotation and Location Invariance. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF
1	Michael von der Beeck, Tiziana Margaria, Bernhard Steffen	A formal requirements engineering method for specification, synthesis, and verification.	SEE	1997	DBLP DOI BibTeX RDF
1	Nur A. Touba, Edward J. McCluskey	Logic synthesis of multilevel circuits with concurrent error detection.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Symbolic two-level minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Jian-Hong Hu, Yao Wang, Patrick T. Cahill	Multispectral code excited linear prediction coding and its application in magnetic resonance images.	IEEE Transactions on Image Processing	1997	DBLP DOI BibTeX RDF
1	Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Analysis and synthesis of concurrent digital circuits using control-flow expressions.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan	Synthesis of initializable asynchronous circuits.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Taewhan Kim, C. L. Liu	An integrated algorithm for incremental data path synthesis.	VLSI Signal Processing	1996	DBLP DOI BibTeX RDF
1	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
1	K. Fuchs	Synthesis for path delay fault testability via tautology-based untestability identification and factorization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	C. Frangos, Y. Yavin	A synthesis procedure for discrete linear time-dependent control systems.	Automatica	1994	DBLP DOI BibTeX RDF
1	Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu	A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	Chen-Huan Chiang, Sandeep K. Gupta	Random pattern testable logic synthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri	Estimating the Complexity of Synthesized Designs from FSM Specifications.	IEEE Design & Test of Computers	1993	DBLP DOI BibTeX RDF
1	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Kwang-Ting Cheng	STOIC: state assignment based on output/input functions.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Chris J. Myers, Teresa H. Y. Meng	Synthesis of timed asynchronous circuits.	IEEE Trans. VLSI Syst.	1993	DBLP DOI BibTeX RDF
1	Anatoly Petrovich Beltiukov	Automatical Synthesis of Programs with Recursions.	Formal Methods in Programming and Their Applications	1993	DBLP DOI BibTeX RDF
1	X. Wang, Edward P. Stabler	Formalization of VHDL Synthesis Procedure in Higher-Order Logic.	TPHOLs	1991	DBLP BibTeX RDF
1	Pranav Ashar, Srinivas Devadas, A. Richard Newton	Irredundant interacting sequential machines via optimal logic synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Khaled M. Elleithy, Magdy A. Bayoumi	A Framework for High Level Synthesis of Digital Architectures from U-Recursive Algorithms.	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
1	Andrzej Krasniewski	Design for verification testability.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Srinivas Devadas, Hi-Keung Tony Ma	Easily testable PLA-based finite state machines.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	A synthesis and optimization procedure for fully and easily testable sequential machines.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Thomas Bergstraesser, Jürgen Gessner, Karlheinz Hafner, Stefan Wallstab	SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture.	DAC	1988	DBLP BibTeX RDF
1	David E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin	Automated layout synthesis in the YASC silicon compiler.	DAC	1986	DBLP DOI BibTeX RDF
1	Ajoy Kumar Datta, Sukumar Ghosh	Modular Synthesis of Deadlock-Free Control Structures.	FSTTCS	1986	DBLP DOI BibTeX RDF	regular nets, Petri nets, synthesis, deadlock