Search results for "system buses"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Mohammad Reza Selim, Takumi Endo, Yuichi Goto, Jingde Cheng	Distributed hash table based design of Soft System Buses.	Infoscale	2007	DBLP DOI BibTeX RDF	chord protocol, soft system bus, middleware, distributed hash table
2	Jingde Cheng	Connecting Components with Soft System Buses: A New Methodology for Design, Development, and Maintenance of Reconfigurable, Ubiquitous, and Persistent Reactive Systems.	AINA	2005	DBLP DOI BibTeX RDF
2	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller	Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.	PATMOS	2000	DBLP DOI BibTeX RDF
1	Kousuke Kawamura, Naoto Mukai	Optimization of Transport Plan for On-Demand Bus System Using Electrical Vehicles.	KES	2009	DBLP DOI BibTeX RDF
1	Takumi Endo, Junichi Miura, Koichi Nanashima, Shoichi Morimoto, Yuichi Goto, Jingde Cheng	Security in Persistently Reactive Systems.	EUC Workshops	2005	DBLP DOI BibTeX RDF
1	Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller	A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller	Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work.	DATE	2004	DBLP DOI BibTeX RDF
1	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller	Low Power Encoding Techniques for Dynamically Reconfigurable Hardware.	The Journal of Supercomputing	2003	DBLP DOI BibTeX RDF	transition minimizing bus encoding, low power, dynamic reconfiguration
1	M. A. Sarwar, Alan D. George, David E. Collins	Reliability Modeling of SCI Ring-Based Topologies. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	SCI ring-based topologies, cluster interconnects, point-to-point ring-based interconnect, switched ring topologies, 1D k-ary n-cube switching fabrics, 2D k-ary n-cube switching fabrics, UltraSAN, single-ring system, redundant ring, fault tolerance, Petri nets, multiprocessor interconnection networks, network topology, reliability modeling, link failures, system buses, multiprocessor interconnects, scalable coherent interface
1	Y. Hayashi, Takashi Matsubara, Yoshiaki Koga	Implementation and evaluation for dependable bus control using CPLD.	PRDC	2000	DBLP DOI BibTeX RDF	phase control, dependable bus control, bus systems, dependable bus operations, bus phase control, reliability, dependability, sequential circuits, system buses, CPLD, asynchronous sequential logic, asynchronous sequential circuit
1	Ehud Finkelstein, Shlomo Weiss	Microprocessor system buses: A case study.	Journal of Systems Architecture	1999	DBLP DOI BibTeX RDF
1	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
1	Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, Yu-Hua Lee	Some Image Processing Algorithms on a RAP with Wider Bus Networks. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	wider bus networks, reconfigurable array of processors, base-m number system, parallel algorithms, parallel algorithms, image processing, image segmentation, image segmentation, parallel architectures, multiprocessor interconnection networks, reconfigurable architectures, histogram, system buses, computation power, image processing algorithms, image labeling, constant time, RAP
1	H. Bekker, E. J. Dijkstra	Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus.	PDP	1996	DBLP DOI BibTeX RDF	delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture
1	M. Li	The cyclic services in an industrial network.	RTCSA	1996	DBLP DOI BibTeX RDF	Profibus, cyclic services, industrial network, polling-interval, system buses
1	Ti-Yen Yen, Wayne Wolf	Communication synthesis for distributed embedded systems.	ICCAD	1995	DBLP DOI BibTeX RDF	analysis algorithm, real-time systems, embedded systems, CAD, distributed processing, distributed embedded systems, interprocess communication, delay bounds, system buses, communication links, co-synthesis, synthesis algorithm, hardware-software co-synthesis
1	Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
1	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
1	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
1	Milan Jovanovic, Milo Tomasevic, Veljko M. Milutinovic	A simulation-based comparison of two reflective memory approaches.	HICSS	1995	DBLP DOI BibTeX RDF	simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data
1	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
1	Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea	Verifying the performance of the PCI local bus using symbolic techniques. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PCI local bus, model checking techniques, performance evaluation, logic testing, system buses, symbolic techniques, timing information, finite-state systems, temporal behavior
1	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
1	Qiang Li, David B. Gustavson	Fat-tree for local area multiprocessors. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	local area multiprocessors, LAMP, high-performance low-cost parallel computing, LAN-size area, remote data cache, high performance multiprocessor, point-to-point physical connections, high system throughput, fat-tree topology, cable length, link clock speeds, biCMOS chips, performance evaluation, parallel architectures, parallel architecture, multiprocessor interconnection networks, local area networks, latency, packet switching, packet switch, CMOS, shared memory systems, distributed memory systems, simulation results, cache storage, system buses, SCI, buffer requirements, distributed-shared-memory multiprocessor, scalable coherent interface
1	Corey Kosak, David A. Eckhardt, Todd W. Mummert, Peter Steenkiste, Allan Fisher	Buffer management and flow control in the Credit Net ATM host interface. (PDF / PS)	LCN	1995	DBLP DOI BibTeX RDF	Credit Net ATM host interface, negotiated quality-of-service guarantees, application-specific data management, network endpoints, PCI bus host adapter architecture, OC-12 ATM, OC-3 ATM, ATM endpoint hosts, asynchronous transfer mode, computer networks, bandwidth, storage management, ATM networking, buffer management, flow control, buffer storage, telecommunication congestion control, system buses
1	Jeffrey A. Floyd, Matt Perry	Real-time on-board bus testing.	VTS	1995	DBLP DOI BibTeX RDF	on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds
1	Syed Masud Mahmud	Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multilevel bus networks, hierarchical multiprocessors, partial multiple bus system, bus architecture, hierarchical multiprocessor design, synchronous multilevel bus systems, asynchronous multilevel bus systems, hierarchical reference model, MVA algorithm, performance evaluation, fault tolerance, performance analysis, parallel architectures, connections, queueing theory, multiprocessing systems, analytical models, bandwidth, queueing networks, switches, simulation models, memory bandwidth, packet-switched networks, cost-effectiveness, system buses, local computations, memory modules
1	Thin-Fong Tsuei, Mary K. Vernon	A Multiprocessor Bus Design Model Validated by System Measurement.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	commercial multiprocessor bus, bus design, asynchronous memorywrite operations, in-order delivery, processor read requests, memoryresponses, outstanding processor requests, two-level hierarchical model, mean value analysis techniques, measured system performance, parallel program workloads, memory access characteristics, analytic queueing models, model tractability, detailed simulation, system design tradeoffs, parallel programming, formal verification, Markov chain, Markov processes, queueing theory, multiprocessing systems, queueing networks, system buses, priority scheduling, performanceevaluation, system measurement
1	Duc J. Vianney, James H. Thomas, Vicki Rabaza	The Gould NP1 system interconnecting.	ICS	1988	DBLP DOI BibTeX RDF	Gould NP1, dual-cpu, processor farm, inter-system bus link, multiprocessor