Search results for "system level power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach	From milliwatts to megawatts: system level power challenge.	DAC	2009	DBLP DOI BibTeX RDF	system level power, system design
2	Manuel Wendt, Matthias Grumer, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger	System level power profile analysis and optimization for smart cards and mobile devices.	SAC	2008	DBLP DOI BibTeX RDF	power profile optimization, system level power estimation, time discrete RF-interface model
2	Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehyuck Chang	System-level power estimation using an on-chip bus performance monitoring unit.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Gerard Bosch i Creus, Petri Niska	System-Level Power Management for Mobile Devices.	CIT	2007	DBLP DOI BibTeX RDF
2	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	System level power estimation methodology with H.264 decoder prediction IP case study.	ICCD	2007	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	System-level power-performance tradeoffs for reconfigurable computing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Considering process variations during system-level power analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	system-on-chip, low power design, process variations, power analysis, power estimation
2	Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine	A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar	Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.	CASES	2003	DBLP DOI BibTeX RDF	reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs
2	Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta	An analysis of system level power management algorithms and theireffects on latency.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Dexin Li, Pai H. Chou, Nader Bagherzadeh	Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems.	VLSI Design	2002	DBLP DOI BibTeX RDF	mode selection, power-aware embedded system, system-level power management
2	Tony Givargis, Frank Vahid, Jörg Henkel	Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF	low power system design, parameterized architectures, system-on-a-chip, intellectual property, cores, system-level modeling
2	Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino	Supporting system-level power exploration for DSP applications.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
2	Lode Nachtergaele, Dennis Moolenaar, Bart Vanhoof, Francky Catthoor, Hugo De Man	System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
2	Chi-Hong Hwang, Allen C.-H. Wu	A predictive system shutdown method for energy saving of event-driven computation.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI circuit design, delay overhead, event-driven computation, exponential-average approach, low delay penalties, pre-wakeup, prediction-miss correction, predictive system shutdown method, sleep mode operations, system-level power management, VLSI, finite state machine, logic CAD, energy saving, power saving, hit ratio, idle period
1	Yang Xu, Rafael Rosales, Bo Wang, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich	A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology.	ARCS	2012	DBLP DOI BibTeX RDF
1	Je-Hoon Lee, Sang-Choon Kim, Young Hwan Kim, Kyoung-Rok Cho	Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Pulkit Grover, Kristen Ann Woyach, Anant Sahai	Towards a Communication-Theoretic Understanding of System-Level Power Consumption.	IEEE Journal on Selected Areas in Communications	2011	DBLP DOI BibTeX RDF
1	Heider Marconi G. Madureira, José Edil G. de Medeiros, José Camargo da Costa, Gilmar S. Beserra	System-level power consumption modeling of a SoC for WSN applications.	NESEA	2011	DBLP DOI BibTeX RDF
1	Miltos D. Grammatikakis, Stratos Politis, Jean-Pierre Schoellkopf, Constantine Papadas	System-level power estimation methodology using cycle- and bit-accurate TLM.	DATE	2011	DBLP DOI BibTeX RDF
1	Jürgen Sommer, Simon Lüders, Stephen Schmitt, Wolfgang Rosenstiel	System-Level Power-Accuracy Trade-Off in Bluetooth Low Energy Networks.	UIC	2011	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser	Hybrid system level power consumption estimation for FPGA-based MPSoC.	ICCD	2011	DBLP DOI BibTeX RDF
1	Pratyush Kumar, Lothar Thiele	System-level power and timing variability characterization to compute thermal guarantees.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Dhiraj K. Pradhan	ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management.	JETC	2010	DBLP DOI BibTeX RDF
1	Pulkit Grover, Kristen Ann Woyach, Anant Sahai	Towards a communication-theoretic understanding of system-level power consumption	CoRR	2010	DBLP BibTeX RDF
1	J. Choi, H. Cha	System-level power management for system-on-a-chip -based mobile devices.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Variation-Aware System-Level Power Analysis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Martin Gag, Tim Wegner, Dirk Timmermann	System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Karthik Ganesan, Jungho Jo, William Lloyd Bircher, Dimitris Kaseridis, Zhibin Yu, Lizy K. John	System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks.	PACT	2010	DBLP DOI BibTeX RDF
1	Soongyu Kwon, Dongjae Song, Seung Wook Lee, Jong Tae Kim	System Level Power Analysis for SoC Architecture Exploration.	PDPTA	2010	DBLP BibTeX RDF
1	Yunxiao Ling, Jun Yi, Chi-Ying Tsui, Wing-Hung Ki	System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee	What's cool for the future of ultra low power designs?	DAC	2010	DBLP DOI BibTeX RDF	system level power, low power, system design
1	Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley Mao	Performance and power modeling in a multi-programmed multi-core environment.	DAC	2010	DBLP DOI BibTeX RDF	performance modeling, assignment, power modeling
1	Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li	Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.	DAC	2010	DBLP DOI BibTeX RDF	low-dropout regulator, on-chip voltage regulation, power delivery network, power efficiency
1	Pinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi	Challenges and methodologies for efficient power budgeting across the die.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	simulation, performance, energy-efficient, management, power, microprocessor, budget
1	Gaurav Dhiman, Tajana Simunic Rosing	System-Level Power Management Using Online Learning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Marco Facchini, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, Paul Marchal	System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.	DATE	2009	DBLP BibTeX RDF
1	John B. Carter	A look inside IBM's green data center research.	ISLPED	2009	DBLP DOI BibTeX RDF	special session, power management, data centers
1	Kenji R. Yamamoto, Paul G. Flikkema	Prospector: Multiscale Energy Measurement of Networked Embedded Systems with Wideband Power Signals.	CSE	2009	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar	Power estimation methodology for a high-level synthesis framework.	ISQED	2009	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy	Coping with Variations through System-Level Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Ankush Varma, Eric Debes, Igor Kozintsev, Paul Klein, Bruce L. Jacob	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt	Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Yuen-Hui Chee, Mike Koplow, Michael Mark, Nathan Pletcher, Mike Seeman, Fred Burghardt, Dan Steingart, Jan M. Rabaey, Paul K. Wright, Seth Sanders	PicoCube: a 1 cm3 sensor node powered by harvested energy.	DAC	2008	DBLP DOI BibTeX RDF	active antennas, advanced packaging, low power, energy management, energy harvesting, intelligent sensors
1	C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen	Test Strategies for Low Power Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Bin Li, Li-Shiuan Peh, Priyadarsan Patra	Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.	NOCS	2008	DBLP DOI BibTeX RDF
1	Diana Marculescu, Jörg Henkel	Guest Editorial Special Section on Low-Power Electronics and Design.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Charles Lefurgy, Xiaorui Wang, Malcolm Allen-Ware	Power capping: a prelude to power shifting.	Cluster Computing	2008	DBLP DOI BibTeX RDF	Power capping, Power shifting, Power budget, Power supplies, Power management, Feedback control, Servers, Provisioning
1	Ankush Varma, Bruce L. Jacob, Eric Debes, Igor Kozintsev, Paul Klein	Accurate and fast system-level power modeling: An XScale-based case study.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, SystemC, Power modeling
1	Fei Gong, Xiaobo Wu	Interactive presentation: System level power optimization of Sigma-Delta modulator.	DATE	2007	DBLP DOI BibTeX RDF
1	Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou	Early Models for System-Level Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
1	Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt	System level clock tree synthesis for power optimization.	DATE	2007	DBLP DOI BibTeX RDF
1	Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti	Throughput of multi-core processors under thermal constraints.	ISLPED	2007	DBLP DOI BibTeX RDF	leakage dependence on temperature, throughput, power, speedup, thermal management, multi-core processors
1	Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li	A programming environment with runtime energy characterization for energy-aware applications.	ISLPED	2007	DBLP DOI BibTeX RDF	energy characterization, energy-aware application, programming environment
1	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	System-on-Chip Power Management Considering Leakage Power Variations.	DAC	2007	DBLP DOI BibTeX RDF
1	Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan	Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.	DAC	2007	DBLP DOI BibTeX RDF
1	Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu	Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip.	DAC	2007	DBLP DOI BibTeX RDF
1	Charles Lefurgy, Xiaorui Wang, Malcolm Allen-Ware	Server-Level Power Control.	ICAC	2007	DBLP DOI BibTeX RDF
1	Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar	Assertion-Based Modal Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
1	Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan	Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho	Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC.	SAMOS	2007	DBLP DOI BibTeX RDF	Platform based SoC, HW/SW co-simulation, verification
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
1	Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	PowerViP: Soc power estimation framework at transaction level.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu	Signature-based workload estimation for mobile 3D graphics.	DAC	2006	DBLP DOI BibTeX RDF	workload estimation, embedded systems, dynamic voltage scaling, 3D graphics
1	Duo Sheng, Ching-Che Chung, Chen-Yi Lee	A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen	Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application.	ICME	2006	DBLP DOI BibTeX RDF
1	Huaxiang Lu, Yan Lu, Zhifang Tang, Shoujue Wang	SOC Dynamic Power Management Using Artificial Neural Network.	ISDA	2006	DBLP DOI BibTeX RDF	ABP, ARBF, Power Management
1	Erik Larsson, Zebo Peng	Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	test set selection, TAM design, power consumption, hot-spots, Test scheduling, design exploration
1	Huaxiang Lu, Yan Lu, Zhifang Tang, Shoujue Wang	SOC Dynamic Power Management Using Artificial Neural Network.	ICNC	2006	DBLP DOI BibTeX RDF
1	Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li	Neurocomputing for Minimizing Energy Consumption of Real-Time Operating System in the System-on-a-Chip.	ICONIP	2006	DBLP DOI BibTeX RDF	SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning
1	Ripal Nathuji, Karsten Schwan	Reducing System Level Power Consumption for Mobile and Embedded Platforms.	ARCS	2005	DBLP DOI BibTeX RDF
1	Koushik Niyogi, Diana Marculescu	System level power and performance modeling of GALS point-to-point communication interfaces.	ISLPED	2005	DBLP DOI BibTeX RDF	mixed clock FIFO, pausible clock, power modeling, globally asynchronous locally synchronous
1	Kuei-Chung Chang, Tien-Fu Chen, Wei-Yen Chuang	System-Level Power-Aware Scheduling by Operation-based Prediction.	PSC	2005	DBLP BibTeX RDF
1	Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li	System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS).	ICCAD	2005	DBLP BibTeX RDF
1	Tilak Agerwala, Siddhartha Chatterjee	Computer Architecture: Challenges and Opportunities for the Next Decade.	IEEE Micro	2005	DBLP DOI BibTeX RDF	system-level power management, application, Computer architecture, workloads, accelerators, system performance, scale-out, power-aware architecture
1	Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan	A power estimation methodology for systemC transaction level models.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	CoreConnect, systemC, power analysis, transaction level models, PowerPC
1	Ripal Nathuji, Balasubramanian Seshasayee, Karsten Schwan	Combining Compiler and Operating System Support for Energy Efficient I/O on Embedded Platforms.	SCOPES	2005	DBLP DOI BibTeX RDF
1	Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka	A Programmable DSP Architecture for Wireless Communication Systems.	ASAP	2005	DBLP DOI BibTeX RDF
1	Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 0002, Felice Balarin	Assertion-Based Design Exploration of DVS in Network Processor Architectures.	DATE	2005	DBLP DOI BibTeX RDF
1	Theodoros Giannopoulos, Vassilis Paliouras	Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Wolfgang Nebel	System-Level Power Optimization.	DSD	2004	DBLP DOI BibTeX RDF
1	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip.	DATE	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
1	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
1	Alireza Mehrnia, Babak Daneshrad	Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM.	ISLPED	2004	DBLP DOI BibTeX RDF	IFIR, multi-rate signal processing, low power design, OFDM, filter bank
1	Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha	System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Krishnan Srinivasan, Karam S. Chatha	An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Efficient power profiling for battery-driven embedded system design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Naehyuck Chang	In-House Tools for Low-Power Embedded Systems.	ICESS	2004	DBLP DOI BibTeX RDF
1	Nicolas Darbel, Yves Rasse, Benoît Jubelin, Martial Carrié	A UMTS-FDD Cell Search Engine.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	UMTS-WCDMA, initial acquisition, digital matched filter, fast hadamard transform, low power architecture
1	Osman S. Unsal, Israel Koren	System-level power-aware design techniques in real-time systems.	Proceedings of the IEEE	2003	DBLP BibTeX RDF
1	Marco Caldari, Massimo Conti, Massimo Coppola, Paolo Crippa, Simone Orcioni, Lorenzo Pieralisi, Claudio Turchetti	System-Level Power Analysis Methodology Applied to the AMBA AHB Bus.	DATE	2003	DBLP DOI BibTeX RDF
1	Dexin Li, Qiang Xie, Pai H. Chou	Scalable modeling and optimization of mode transitions based on decoupled power management architecture.	DAC	2003	DBLP DOI BibTeX RDF	compex system, component mode, mode change, mode transition, power management, power model
1	Curt Schurgers, Vijay Raghunathan, Mani B. Srivastava	Power management for energy-aware communication systems.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	adaptive, Energy-efficient, wireless communications, scaling
1	Jinggang Wang, Binoy Ravindran, Tom Martin	A Power-Aware, Best-Effort Real-Time Task Scheduling Algorithm.	WSTFEUS	2003	DBLP DOI BibTeX RDF
1	Tony Givargis, Frank Vahid, Jörg Henkel	Instruction-based system-level power evaluation of system-on-a-chip peripheral cores.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy	System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.	ISSS	2002	DBLP DOI BibTeX RDF	voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
1	Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Fast system-level power profiling for battery-efficient system design.	CODES	2002	DBLP DOI BibTeX RDF
1	Kanishka Lahiri, Sujit Dey, Anand Raghunathan	Communication architecture based power management for battery efficient system design.	DAC	2002	DBLP DOI BibTeX RDF	battery efficiency, embedded systems, low power design, power management, communication architectures
1	Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz	The Minimax Cache: An Energy-Efficient Framework for Media Processors.	HPCA	2002	DBLP DOI BibTeX RDF	media-sensitive caching, compiler- architecture interaction, energy-efficient architectures