Search results for "system-level optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Dennis B. Mulcare	System-level optimization of architectural performance under varying service demands.	ECBS	1996	DBLP DOI BibTeX RDF	system-level optimization, architectural performance, varying service demands, cost-performance measures, dynamic performance, varying workload, system resource parameters, architecture parameters, online transaction processing system, fitness metric, fitness ranking, multiple mutation operator mechanism, genetic algorithms, genetic algorithm, optimization, distributed processing, convergence, system design, systems analysis, performance measures, transaction processing, software performance evaluation, software prototyping, tolerances, online operation, chromosome, distributed system architectures
2	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	vlsi design, task allocation, multiprocessor systems-on-chip
2	Yaxuan Qi, Baohua Yang, Bo Xu, Jun Li	Towards System-level Optimization for High Performance Unified Threat Management.	ICNS	2007	DBLP DOI BibTeX RDF
1	Sungho Yun, Constantine Caramanis	System-Level Optimization in Wireless Networks: Managing Interference and Uncertainty via Robust Optimization.	IEEE/ACM Trans. Netw.	2012	DBLP DOI BibTeX RDF
1	Nan Wang, Lin Wang, Yanlong Bu, Guozhong Zhang, Lincheng Shen	Tactical Aircraft Pop-Up Attack Planning Using Collaborative Optimization.	ICIC	2009	DBLP DOI BibTeX RDF	pop-up attack, weapon delivery, collaborative optimization, planning, law, response surface
1	Daw-Tung Lin, Chung-Yu Yang	H.264/AVC Video Encoder Realization and Acceleration on TI DM642 DSP.	PSIVT	2009	DBLP DOI BibTeX RDF	H.264/AVC encoder, TM320DM642 DSP, optimization, motion estimation, quantization, mode decision
1	Charles-Antoine Robelin, Samer M. Madanat	Reliability-Based System-Level Optimization of Bridge Maintenance and Replacement Decisions.	Transportation Science	2008	DBLP DOI BibTeX RDF
1	Guo Yu, Peng Li	Yield-aware hierarchical optimization of large analog integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma	Interconnect modeling for improved system-level design optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Hong-Zhong Huang, Ye Tao, Yu Liu	Multidisciplinary collaborative optimization using fuzzy satisfaction degree and fuzzy sufficiency degree model.	Soft Comput.	2008	DBLP DOI BibTeX RDF	Collaborative optimization, Fuzzy satisfaction degree, Fuzzy sufficiency degree, Multidisciplinary design optimization
1	Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris	Application - specific NoC platform design based on System Level Optimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla	VT Matrix Multiply Design for MEMOCODE '07.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Assim Sagahyroon	Power Consumption in Handheld Computers.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen	Fast and efficient voltage scheduling by evolutionary slack distribution.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Jingzhao Ou, Viktor K. Prasanna	A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms.	FPL	2004	DBLP DOI BibTeX RDF
1	Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha	High-Level Energy Estimation for ARM-Based SOCs.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Ray Odaira, Kei Hiraki	Selective Optimization of Locks by Runtime Statistics and Just-in-Time Compilation.	IPDPS	2003	DBLP DOI BibTeX RDF	runtime statistics, mutex lock, Java, JVM, runtime optimization
1	Kazuo Sakiyama, Patrick Schaumont, David Hwang, Ingrid Verbauwhede	Teaching Trade-offs in System-level Design Methodologies.	MSE	2003	DBLP DOI BibTeX RDF
1	Francesco Papariello, Gabriele Luculli	Optimization of a Retargetable Functional Simulator for Embedded Processors. (PDF / PS)	ECBS	2002	DBLP DOI BibTeX RDF	retargetable ISS, platform design, system-on-chip, embedded processors, system-level design
1	Ansgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz	System level optimization and design space exploration for low power.	ISSS	2001	DBLP BibTeX RDF
1	Amr G. Wassal, M. Anwar Hasan	Low-power system-level design of VLSI packet switching fabrics.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF