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Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Vamsi Krishna, Abdel Ejnioui, N. Ranganathan |
A tree matching chip.  |
VLSI Design  |
1996 |
DBLP DOI BibTeX RDF |
tree matching chip, online interpreter systems, linear systolic array algorithms, fixed size linear array, Cadence design tools, parallel algorithms, VLSI, compilers, object recognition, image recognition, systolic arrays, digital signal processing chips, code optimization, 3D object recognition, vision systems, systolic architecture |
| 2 | Oscar H. Ibarra, Stephen M. Sohn |
On Mapping Systolic Algorithms onto the Hypercube.  |
IEEE Trans. Parallel Distrib. Syst.  |
1990 |
DBLP DOI BibTeX RDF |
parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation |
| 1 | Michael Penner, Viktor K. Prasanna |
Cache-Friendly implementations of transitive closure.  |
ACM Journal of Experimental Algorithmics  |
2006 |
DBLP DOI BibTeX RDF |
Floyd-Warshall algorithm, systolic array algorithms, Data structures |
| 1 | P. K. Mishra |
Optimal systolic array algorithms for tensor product.  |
Applied Mathematics and Computation  |
2005 |
DBLP DOI BibTeX RDF |
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