Search results for "systolic arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
3	Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko	Near Real Time Enhancement of Remote Sensing Imagery Based on a Network of Systolic Arrays.	CIARP	2009	DBLP DOI BibTeX RDF	Network of Systolic Arrays, Remote Sensing, Hardware/Software Co-Design
3	Minesh I. Patel, N. Ranganathan	A VLSI System Architecture For Real-Time Intelligent Decision Making.	ASAP	1996	DBLP DOI BibTeX RDF	VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays
3	Chein-Wei Jen, Ding-Ming Kwai	Data Flow Representation of Iterative Algorithms for Systolic Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	data flow representation, algebraic representation, modeling, parallel architectures, systolic arrays, systolic arrays, digital arithmetic, generating function, iterative algorithms, dependence graph, power series, geometric representation
3	Yiwan Wong, Jean-Marc Delosme	Optimization of Computation Time for Systolic Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple functional units, pipelined functional units, computation time minimization, linear scheduling function, bounded search space, parallel algorithms, concurrency, multiprocessor interconnection networks, systolic arrays, systolic arrays, minimisation, combinatorial optimization problem, branch-and-bound method
3	Viktor K. Prasanna, Yu-Chen Tsai	On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	optimal family of linear systolic arrays, local storage, fault wafer scale integration models, VLSI, delay, systolic arrays, matrix multiplication, circuit layout CAD, processing elements
3	Viktor K. Prasanna, Yu-Chen Tsai	On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, linearly connected arrays, processor elements, VLSI model, Diogenes methodology, algorithms, fault tolerant computing, cellular arrays, propagation delay, matrix computations, mapping technique, linear systolic arrays
3	Catherine Mongenet, Guy-René Perrin	Synthesis of Systolic arrays for Inductive Problems.	PARLE	1987	DBLP DOI BibTeX RDF	synthesis, systolic arrays
2	Roger F. Woods, John V. McCanny, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	SoC architectures, DSP systems, pipelining, systolic arrays
2	A. Neslin Ismailoglu, Murat Askar	SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.	DSD	2008	DBLP DOI BibTeX RDF
2	Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain	Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs.	ASAP	2008	DBLP DOI BibTeX RDF
2	Laura Ruff	Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays.	SYNASC	2007	DBLP DOI BibTeX RDF
2	Qin Wang, Ang Li, Zhancai Li, Yong Wan	A Design and Implementation of Reconfigurable Architecture for Neural Networks Based on Systolic Arrays.	ISNN	2006	DBLP DOI BibTeX RDF
2	Aasavari Bhave, Eurípides Montagne, Edgar Granados	Describing Quantum Circuits with Systolic Arrays.	ASAP	2006	DBLP DOI BibTeX RDF
2	Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
2	M. Ch. Karra, M. P. Bekakos	A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method.	The Journal of Supercomputing	2006	DBLP DOI BibTeX RDF	FPGA technology, parallelism, finite-state machine, time complexity, systolic arrays, processing elements
2	Yun Yang, Wenqing Zhao, Yasuaki Inoue	High-performance systolic arrays for band matrix multiplication.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2m) for High Speed Cryptographic Processors.	ICCSA	2005	DBLP DOI BibTeX RDF	VLSI, finite field, systolic array, irreducible trinomial
2	Ján Glasa	On Bit-Level Systolic Arrays for Least-Squares Digital Contour Smoothing.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
2	Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein	Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic.	SBCCI	2004	DBLP DOI BibTeX RDF	configware, morphware, reconfigurable systolic arrays, term rewriting systems (TRS), dynamic programming, rewriting-logic
2	Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye	Switched Memory Architectures-Moving Beyond Systolic Arrays.	ASAP	2003	DBLP DOI BibTeX RDF
2	Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments.	SCCC	2003	DBLP DOI BibTeX RDF	Reconfigurable Systolic Arrays, Fast Fourier Transform, Rewriting-Logic, Term Rewriting Systems
2	Sek M. Chai, D. Scott Wills	Systolic Opportunities for Multidimensional Data Streams.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	area I/O, design and performance evaluation, systolic arrays, parallel computer architecture
2	Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye	Quadratic Control Signals in Linear Systolic Arrays.	ASAP	2000	DBLP DOI BibTeX RDF	multidimensional time, control signal, systolic array
2	William L. Freking, Keshab K. Parhi	Performance-Scalable Array Architectures for Modular Multiplication.	ASAP	2000	DBLP DOI BibTeX RDF	high-radix algorithms, cylindrical arrays, folding transformation, systolic arrays, modular multiplication, scalable architectures
2	Colin D. Walter	Montgomery's Multiplication Technique: How to Make It Smaller and Faster.	CHES	1999	DBLP DOI BibTeX RDF	higher radix methods, checker function, fault tolerance, testing, cryptography, RSA, Computer arithmetic, systolic arrays, error correction, differential power analysis, DPA, Montgomery modular multiplication
2	I. M. Bland, Graham M. Megson	The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology.	FCCM	1998	DBLP DOI BibTeX RDF
2	Karl-Heinz Zimmermann	A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP.	VLSI Signal Processing	1997	DBLP DOI BibTeX RDF
2	Eberhard Zehendner	Simulating Systolic Arrays on MasPar Machines.	EUROMICRO	1997	DBLP DOI BibTeX RDF
2	Rumen Andonov, Sanjay V. Rajopadhye	Knapsack on VLSI: from Algorithm to Optimal Circuit.	IEEE Trans. Parallel Distrib. Syst.	1997	DBLP DOI BibTeX RDF	Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays
2	Karl-Heinz Zimmermann	Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays.	VLSI Signal Processing	1996	DBLP DOI BibTeX RDF
2	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Area efficient computing structures for concurrent error detection in systolic arrays.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
2	Cheng-Wen Wu, Ming-Kwang Chang	Bit-level systolic arrays for finite-field multiplications.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
2	Dominique Lavenier, Frédéric Raimbault, Patrice Frison	I/O and computation overlap on SIMD systolic arrays.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
2	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
2	E. Pascal Gribomont, Vincent Van Dongen	Generic Systolic Arrays: A Methodology for Systolic Design.	TAPSOFT	1993	DBLP DOI BibTeX RDF
2	David Naylor, Simon Jones	A Model Based Approach to the Performance Analysis of Multi-Layer Networks Realised in Linear Systolic Arrays.	IWANN	1993	DBLP DOI BibTeX RDF
2	Edwin Hsing-Mean Sha, Kenneth Steiglitz	Reconfigurability and Reliability of Systolic/Wavefront Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs
2	Andrew Spray, Simon Jones	Performance Tradeoffs in Rings of Data-Driven Elements.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	performance tradeoffs, data-driven elements, maintaining causality, medium grained cellular based architectures, data-driven communication, hardware simplicity, throughput rate, globally checked systolic arrays, performance evaluation, latency, systolic arrays, rings
2	Guu-chang Yang, Thomas E. Fuja	The Reliability of Systems with Two Levels of Fault Tolerance: The Return of the "Birthday Surprise".	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	chip level coding, hierarchical levels, random access memory systems, board-level coding, fault-tolerant systolic arrays, fault tolerance, reliability, fault tolerant computing, encoding, systolic arrays, random-access storage, two-dimensional array
2	Marios D. Dikaiakos, Kenneth Steiglitz	Comparison of tree and straight-line clocking for long systolic arrays.	VLSI Signal Processing	1991	DBLP DOI BibTeX RDF
2	Hervé Le Verge, Christophe Mauras, Patrice Quinton	The ALPHA language and its use for the design of systolic arrays.	VLSI Signal Processing	1991	DBLP DOI BibTeX RDF
2	Xiaoxiong Zhong, Sanjay V. Rajopadhye	Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions.	PARLE	1991	DBLP DOI BibTeX RDF
2	Jang-Ping Sheu, Chih-Yung Chang	Synthesizing Nested Loop Algorithms Using Nonlinear Transformation Method.	IEEE Trans. Parallel Distrib. Syst.	1991	DBLP DOI BibTeX RDF	nested loop algorithms, nonlinear transformation method, FOR-loop models, nestedFOR-loops, fixed size systolic arrays, space mapping schemes, parallelform, parallel algorithms, parallel programming, array processors
2	Jean Frédéric Myoupo	A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems.	ICCI	1991	DBLP DOI BibTeX RDF	Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays
2	A. Majumdar, C. S. Raghavendra, Melvin A. Breuer	Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	triple time redundancy, gracefully degradable mode, fault tolerant computing, logic testing, reconfiguration, throughput, interconnection, switching, performance metrics, cellular arrays, running time, reliability analysis, control structures, fault-tolerant capabilities, linear systolic arrays
2	W. Scott Stornetta, Bernardo A. Huberman, Tad Hogg	Scaling theory for fault stealing algorithms in large systolic arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Nam Ling, Magdy A. Bayoumi	Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Paul Molitor	Constrained via minimization for systolic arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Richard Hughey, Daniel P. Lopresti	A software approach to fault detection on programmable systolic arrays.	SPDP	1990	DBLP DOI BibTeX RDF
2	Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri	Design of optimal systolic arrays: a systematic approach.	SPDP	1990	DBLP DOI BibTeX RDF
2	Oscar H. Ibarra, Stephen M. Sohn	On Mapping Systolic Algorithms onto the Hypercube.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
2	Hon Fung Li, R. Jayakumar, Clement Wing Hong Lam	Restructuring for Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, faulty cells, data-flow paths, computational sites, programmable delays, fault tolerant computing, cellular arrays, restructuring, processing elements, data skewing
2	Clement Wing Hong Lam, Hon Fung Li, R. Jayakumar	A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	faulty systolic arrays, faulty cells, square array, minimal fault pattern, fault tolerance, fault tolerant computing, redundancy, redundancy, cellular arrays
2	James L. Olivier, Füsun Özgüner	Design of concurrent error-detecting systolic arrays using \|g 3N\|M codes.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
2	Norihiko Yoshida	Transformational Derivation of Systolic Arrays.	Concurrency: Theory, Language, And Architecture	1989	DBLP DOI BibTeX RDF
2	Juraj Hromkovic, Juraj Procházka	Branching Programs as a Tool for Proving Lower Bounds on VLSI Computations and Optimal Algorithms for Systolic Arrays.	MFCS	1988	DBLP DOI BibTeX RDF
2	E. Pascal Gribomont	Proving Systolic Arrays.	CAAP	1988	DBLP DOI BibTeX RDF
2	Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas	Translating systolic arrays into instruction systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE
2	Alice A. McRae, Keith A. R. Allen, Roy P. Pargas	Comparison of several techniques for generating systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE, SAGE
2	Patrick M. Lenders	A Generalized Message-Passing Mechanism for Communicating Sequential Processes.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	bidirectional message passing, generalized message-passing mechanism, symmetric communication mechanism, CSP-like syntax, weakest-precondition semantics, parallel processing, synchronization, distributed processing, systolic arrays, systolic arrays, trees (mathematics), tree structure, communicating sequential processes, concurrent processes, communication primitives
2	Nikrouz Faroughi, Michael A. Shanblatt	An Improved Systematic Method for Constructing Systolic Arrays from Algorithms.	DAC	1987	DBLP DOI BibTeX RDF
2	Sunil Ashtaputre, Carla D. Savage	Systolic Arrays with Embedded Tree Structures for Connectivity Problems.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	pipelining, trees, systolic arrays, Graph connectivity, UNION-FINDS
1	Alejandro Castillo Atoche, J. Estrada Lopez, R. Quijano Cetina, L. Rizo Dominguez	Efficient Design of Bit-level Accelerator Architectures for the DEDR-RASF Remote Sensing Algorithm using Super-systolic Arrays.	PECCS	2012	DBLP BibTeX RDF
1	Igor Z. Milovanovic, Emina I. Milovanovic, Mile K. Stojcev	A class of fault-tolerant systolic arrays for matrix multiplication.	Mathematical and Computer Modelling	2011	DBLP DOI BibTeX RDF
1	Ni-Chun Wang, Ezio Biglieri, Kung Yao	Systolic arrays for lattice-reduction-aided mimo detection.	Journal of Communications and Networks	2011	DBLP DOI BibTeX RDF
1	Igor Z. Milovanovic, Emina I. Milovanovic, Mile K. Stojcev, M. P. Bekakos	Orthogonal fault-tolerant systolic arrays for matrix multiplication.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Ni-Chun Wang, Ezio Biglieri, Kung Yao	Systolic Arrays for Lattice-Reduction-Aided MIMO Detection	CoRR	2011	DBLP BibTeX RDF
1	James Reinders	Systolic Arrays.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1		Instruction Systolic Arrays.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Stefan Gruner, T. J. Steyn	Deadlock-freeness of hexagonal systolic arrays.	Inf. Process. Lett.	2010	DBLP DOI BibTeX RDF
1	Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko	Towards real time implementation of reconstructive signal processing algorithms using systolic arrays coprocessors.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Richard P. Brent, Franklin T. Luk, H. T. Kung	Some linear-time algorithms for systolic arrays	CoRR	2010	DBLP BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
1	Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
1	Emina I. Milovanovic, M. P. Bekakos, Igor Z. Milovanovic	Synthesis of space optimal systolic arrays for band matrix-vector multiplication.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF
1	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	More efficient systolic arrays for multiplication in GF(2m) using LSB first algorithm with irreducible polynomials and trinomials.	Computers & Electrical Engineering	2009	DBLP DOI BibTeX RDF
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Optimal runtime reconfiguration strategies for systolic arrays.	FPL	2009	DBLP DOI BibTeX RDF
1	Halil Snopce, Ilir Spahiu	An implementation of MacMahon's partition analysis in ordering the number of lattice points in convex polyhedron with examples for systolic arrays.	ITI	2009	DBLP DOI BibTeX RDF
1	M. Manjunathaiah	Hierarchical Composite Regular Parallel Architecture.	ISPDC	2009	DBLP DOI BibTeX RDF	systolic arrays, space-time mapping
1	Rafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman	A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks.	ReConFig	2009	DBLP DOI BibTeX RDF	multivariate polynomial interpolation, parameterizable architectures, bioinformatic applications, reverse engineering problem for gene networks, systolic arrays
1	Sudhir Vinjamuri, Viktor K. Prasanna	Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors.	PaCT	2009	DBLP DOI BibTeX RDF	systolic array designs, parallel programming, high performance computing, multicore, dependency graphs
1	Anas N. Al-Rabadi	Reversible Systolic Arrays: M-Ary Bijective Single-Instruction Multiple-Data (SIMD) Architectures and their Quantum Circuits.	Journal of Circuits, Systems, and Computers	2008	DBLP DOI BibTeX RDF
1	Betul Buyukkurt, Walid A. Najjar	Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
1	Alexandre Abellard, Patrick Abellard	A Design Methodology of Systolic Architectures Based on a Petri Net Extension. Application to a Stereovision Hardware/Software Processing Improvement.	ICSEA	2008	DBLP DOI BibTeX RDF
1	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Peter R. Cappello	Application-specific Processor Architecture: Then and Now.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	field-programmable gate array, FPGA, computer architecture, taxonomy, systolic array, processor array, application-specific processor, general-purpose processor
1	Kung Yao, Flavio Lorenzelli	Systolic Algorithms and Architectures for High-Throughput Processing Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	recursive least-squares estimation, Kalman filtering, systolic array, linear algebra, QR decomposition, least-squares estimation
1	Emina I. Milovanovic, Igor Z. Milovanovic, M. P. Bekakos, I. N. Tselepis	Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform.	The Journal of Supercomputing	2007	DBLP DOI BibTeX RDF	FPGA, Parallel computations, Systolic arrays, All-pairs shortest paths, Parallel iterative methods
1	Clémentin Tayou Djamégni	Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules.	J. Parallel Distrib. Comput.	2006	DBLP DOI BibTeX RDF
1	John V. McCanny, Roger F. Woods, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	ASAP	2006	DBLP DOI BibTeX RDF
1	Nuha A. S. Alwan	A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Trigonometric series, sinusoidal sequence generation, pipelining, systolic arrays
1	Ozgur Tamer, Ahmet Özkurt	Systolic Array Based Adaptive Beamformer Modeling in SystemC Environment.	AHS	2006	DBLP DOI BibTeX RDF
1	A. K. Das, S. K. Ghosh	A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Pramod Kumar Meher	Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation.	IEEE Trans. Circuits Syst. Video Techn.	2006	DBLP DOI BibTeX RDF
1	Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen	Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	global elimination algorithm, motion estimation, VLSI architecture, block matching
1	Amir K. Daneshbeh, M. Anwarul Hasan	A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2m).	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field arithmetic, finite fields, systolic arrays, Division, inversion, extended Euclidean algorithm
1	Tudor Jebelean, Laura Szakacs	Functional-Based Synthesis of Systolic Online Multipliers.	SYNASC	2005	DBLP DOI BibTeX RDF
1	Hajime Matsui, S. Sakata, M. Kurihara, Seiichi Mita	Systolic array architecture implementing Berlekamp-Massey-Sakata algorithm for decoding codes on a class of algebraic curves.	IEEE Transactions on Information Theory	2005	DBLP DOI BibTeX RDF
1	Jacek Mazurkiewicz	Systolic Realization of Kohonen Neural Network.	ICANN	2005	DBLP DOI BibTeX RDF