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Results
Found 23 publication records. Showing 23 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy |
Compact thermal modeling for temperature-aware design.  |
DAC  |
2004 |
DBLP DOI BibTeX RDF |
temperature-aware computing, reliability, leakage, thermal model, temperature-aware design, power-aware design |
| 2 | Wei Huang, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan |
Differentiating the roles of IR measurement and simulation for power and temperature-aware design.  |
ISPASS  |
2009 |
DBLP DOI BibTeX RDF |
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| 2 | Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini |
Exploring "temperature-aware" design in low-power MPSoCs.  |
DATE  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Ayse Kivilcim Coskun, David Atienza, Mohamed M. Sabry, Jie Meng |
Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling.  |
IEEE Micro  |
2011 |
DBLP DOI BibTeX RDF |
active cooling, 3D liquid-cooled systems, multiprocessor systems, emerging technologies, energy-aware systems, temperature-aware design |
| 1 | Yousra Alkabani, Farinaz Koushanfar, Miodrag Potkonjak |
N-version temperature-aware scheduling and binding.  |
ISLPED  |
2009 |
DBLP DOI BibTeX RDF |
N-variants, high-level synthesis, temperature control |
| 1 | Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, Paulo J. Teixeira |
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.  |
J. Low Power Electronics  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, Mircea R. Stan |
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model.  |
IEEE Trans. Computers  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Wei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron |
Many-core design from a thermal perspective.  |
DAC  |
2008 |
DBLP DOI BibTeX RDF |
many-core design, thermal design power, performance, temperature |
| 1 | Swarup Bhunia, Kaushik Roy |
Low power design under parameter variations.  |
SoCC  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick |
Application-Specific MPSoC Reliability Optimization.  |
IEEE Trans. VLSI Syst.  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida |
HW-SW emulation framework for temperature-aware design in MPSoCs.  |
ACM Trans. Design Autom. Electr. Syst.  |
2007 |
DBLP DOI BibTeX RDF |
Thermal-aware design, FPGA, emulation, MPSoC, temperature |
| 1 | Giacomo Paci, Francesco Poletti, Luca Benini, Paul Marchal |
Exploring temperature-aware design in low-power MPSoCs.  |
IJES  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami |
The effect of temperature on cache size tuning for low energy embedded systems.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, cache memory, low energy, leakage current, temperature-aware design |
| 1 | Kimish Patel, Wonbok Lee, Massoud Pedram |
Active bank switching for temperature control of the register file in a microprocessor.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
register file, thermal model, temperature-aware design |
| 1 | Yan Zhang, Mircea R. Stan |
Temperature-aware circuit design using adaptive body biasing.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, temperature-aware design |
| 1 | Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose |
Thermal-aware task scheduling at the system software level.  |
ISLPED  |
2007 |
DBLP DOI BibTeX RDF |
low-power design, repeater insertion, temperature-aware design |
| 1 | Ja Chun Ku, Yehea I. Ismail |
Thermal-aware methodology for repeater insertion in low-power VLSI circuits.  |
ISLPED  |
2007 |
DBLP DOI BibTeX RDF |
low-power design, repeater insertion, temperature-aware design |
| 1 | Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou |
Low-Power Design and Temperature Management.  |
IEEE Micro  |
2007 |
DBLP DOI BibTeX RDF |
low-power design, power management, hardware, energy-aware systems, temperature-aware design |
| 1 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic thermal clock skew compensation using tunable delay buffers.  |
ISLPED  |
2006 |
DBLP DOI BibTeX RDF |
temperature aware design methodology, tunable delay buffers, clock skew, clock tree |
| 1 | Wonbok Lee, Kimish Patel, Massoud Pedram |
Dynamic thermal management for MPEG-2 decoding.  |
ISLPED  |
2006 |
DBLP DOI BibTeX RDF |
MPEG-2 decoding, thermal model, temperature-aware design |
| 1 | Wei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan |
The need for a full-chip and package thermal model for thermally optimized IC designs.  |
ISLPED  |
2005 |
DBLP DOI BibTeX RDF |
leakage, package, thermal model, temperature-aware design |
| 1 | Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee |
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.  |
DAC  |
2004 |
DBLP DOI BibTeX RDF |
electrothermal couplings, temperature aware design, subthreshold leakage, energy delay product |
| 1 | Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan |
Temperature-Aware Computer Systems: Opportunities and Challenges.  |
IEEE Micro  |
2003 |
DBLP DOI BibTeX RDF |
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