Search results for "test application"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
3	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	scan circuits, test application time, static test compaction
3	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
3	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators.	VTS	2000	DBLP DOI BibTeX RDF	Built-in-Self-Test, Test Generation, Combinational Circuits, Test Application Time, Stuck-at Fault Model
3	Zdenek Kotásek, F. Zboril	RT level testability analysis to reduce test application time.	EUROMICRO	1997	DBLP DOI BibTeX RDF	register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
3	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
3	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
3	Bapiraju Vinnakota, Nicholas J. Stessman	Reducing test application time in scan design schemes.	VTS	1995	DBLP DOI BibTeX RDF	scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
3	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
2	Ho Fai Ko, Nicola Nicolici	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Skewed-load, Scan division, At-speed test, Low-power test
2	Rohit Kapur, Subhasish Mitra, Thomas W. Williams	Historical Perspective on Scan Compression.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	scan compression, test data volume reduction, IC testing, test application time reduction
2	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
2	Anshuman Chandra, Haihua Yan, Rohit Kapur	Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.	VTS	2007	DBLP DOI BibTeX RDF
2	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	European Test Symposium	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
2	M. Shah, D. Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	On reducing test application time for scan circuits using limited scan operations and transfer sequences.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.	PRDC	2005	DBLP DOI BibTeX RDF
2	Themistoklis Haniotakis, Spyros Tragoudas, G. Pani	Reduced Test Application Time Based on Reachability Analysis.	ISQED	2005	DBLP DOI BibTeX RDF
2	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	Partial Gating Optimization for Power Reduction During Test Application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue	A Huffman-based coding with efficient test application.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma	Reconfigurable multiple scan-chains for reducing test application time of SOCs.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
2	Anshuman Chandra, Krishnendu Chakrabarty	Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, system-on-a-chip testing, test set encoding, variable-to-variable-length codes, automatic test equipment (ATE), testing time, embedded core testing
2	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.	ISQED	2004	DBLP DOI BibTeX RDF
2	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy	A Technique to Reduce Power and Test Application Time in BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Scan circuits, test application time, static test compaction
2	Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz	On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.	ITC	2003	DBLP DOI BibTeX RDF
2	Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara	A DFT Selection Method for Reducing Test Application Time of System-on-Chips.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	wrapper, design for test, test scheduling, test access mechanism
2	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
2	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
2	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
2	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Power profile manipulation: a new approach for reducing test application time under power constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Kuen-Jong Lee, Jih-Jeen Chen	Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici	Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.	DATE	2002	DBLP DOI BibTeX RDF
2	Wei-Lun Wang, Kuen-Jong Lee	An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	mixed-mode pattern generation, built-in self-test, power consumption, test application time, scan chain
2	Ozgur Sinanoglu, Alex Orailoglu	Compaction Schemes with Minimum Test Application Time.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
2	Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta	Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Xiaowei Li, Huawei Li, Yinghua Min	Reducing Power Dissipation during At-Speed Test Application. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Test-pair Ordering, Power Dissipation, At-speed Test
2	Irith Pomeranz, Sudhakar M. Reddy	On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
2	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
2	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
2	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
2	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
2	Irith Pomeranz, Sudhakar M. Reddy	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	synchronous sequential circuits, test application time, Static test compaction
2	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	design-for-testability, BIST, scan design
2	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
2	Nicola Nicolici, Bashir M. Al-Hashimi	Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.	DATE	1999	DBLP DOI BibTeX RDF
2	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Full Scan Embedded Cores.	FTCS	1999	DBLP DOI BibTeX RDF	test generation, design-for-testability, fault simulation, embedded cores, full scan
2	Albrecht P. Stroele, Frank Mayer	Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	loop folding, test configuration, test register, built-in self-test, test schedule, test application time, Accumulator
2	Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy	Techniques for minimizing power dissipation in scan and combinational circuits during test application.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
2	Xiao Sun, Carmie Hull	Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
2	Albrecht P. Stroele, Frank Mayer	Methods to reduce test application time for accumulator-based self-test.	VTS	1997	DBLP DOI BibTeX RDF	accumulator-based self-test, test length minimization, simulation-based reseeding method, random pattern testable circuits, reverse order simulation, hard fault detection, optimal input value, test length reductions, data path blocks, BIST scheme, ATALANTA fault simulation, combinatorial circuit testing, built-in self test, fault coverage, embedded processor, test pattern generators, circuit optimization, test application time reduction, forward simulation
2	Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham	Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.	VTS	1996	DBLP DOI BibTeX RDF	waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
2	Dhiraj K. Pradhan, Jayashree Saxena	A novel scheme to reduce test application time in circuits with full scan.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Soo Young Lee, Kewal K. Saluja	Test application time reduction for sequential circuits with scan.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
2	S. Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
2	J. A. Lupo	Benchmarking UHGROMOS.	HICSS	1995	DBLP DOI BibTeX RDF	GROMOS, parallel Fortran preprocessor, Pfortran, Intel Corporation, IBM Corporation, massively parallel processor machines, Intel iPSC/860, Caltech Intel DELTA, IBM SP1, UHGROMOS molecular dynamics program, test application, parallel performance analysis, parallel programming, benchmarking, FORTRAN, parallel machines, parallel machines, software performance evaluation, physics, parallel languages, software portability, physics computing, porting, Intel Paragon, program processors, molecular dynamics method
2	Xinli Gu	RT level testability-driven partitioning.	VTS	1995	DBLP DOI BibTeX RDF	testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
2	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
2	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
2	Claudio Costi, Micaela Serra, Donatella Sciuto	A new DFT methodology for sequential circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	design for testability, ATPG, fault coverage, scan design, test application time
2	Hideo Fujiwara, Akihiro Yamamoto	Parity-scan design to reduce the cost of test application.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Vijay S. Iyengar, Gopalakrishnan Vijayan	Optimized test application timing for AC test.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
1	Ender Yilmaz, Sule Ozev	Test Application for Analog/RF Circuits With Low Computational Burden.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Claude Thibeault, Yassine Hariri, C. Hobeika	Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue	Hybrid Test Application in Partial Skewed-Load Scan Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Katherine Shu-Min Li, Jr-Yang Huang	Synthesizing Multiple Scan Trees to Optimize Test Application Time.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur	Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C).	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty	Power-safe test application using an effective gating approach considering current limits.	VTS	2011	DBLP DOI BibTeX RDF
1	Zhen Chen, Dong Xiang	A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Chiba Scan Delay Fault Testing with Short Test Application Time.	J. Electronic Testing	2010	DBLP DOI BibTeX RDF
1	Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee	Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead.	J. Electronic Testing	2010	DBLP DOI BibTeX RDF
1	Qingfeng Guan, Keith C. Clarke	A general-purpose parallel raster processing programming library test application using a geographic cellular automata model.	International Journal of Geographical Information Science	2010	DBLP DOI BibTeX RDF
1	Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara	Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue	Hybrid test application in hybrid delay scan design.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh	On Minimization of Test Application Time for RAS.	VLSI Design	2010	DBLP DOI BibTeX RDF	Random Access Scan (RAS), DFT, Scan Design
1	A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh	Test application time minimization for RAS using basis optimization of column decoder.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel	The Use of Genetic Algorithm to Reduce Power Consumption during Test Application.	ICES	2010	DBLP DOI BibTeX RDF
1	Jirí Simácek, Lukás Sekanina, Lukás Starecek	Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time.	ICES	2010	DBLP DOI BibTeX RDF
1	Narayan Ramasubbu, Rajesh Krishna Balan	Evolution of a bluetooth test application product line: a case study.	SIGSOFT FSE	2010	DBLP DOI BibTeX RDF
1	YongJoon Kim, Myung-Hoon Yang, Jaeseok Park, Eunsei Park, Sungho Kang	Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time.	IEICE Transactions	2009	DBLP BibTeX RDF
1	José M. Solana	Reducing test application time, test data volume and test power through Virtual Chain Partition.	Integration	2009	DBLP DOI BibTeX RDF
1	Michael S. Hsiao, Mainak Banga	Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF	TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
1	Spandana Remarsu, Sandip Kundu	On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	self compensating comparator, dithering, thermal sensor
1	Mouna Ayari, Zeinab Movahedi, Guy Pujolle, Farouk Kamoun	ADMA: autonomous decentralized management architecture for MANETs: a simple self-configuring case study.	IWCMC	2009	DBLP DOI BibTeX RDF	ADMA, DPMP, ad hoc networks, VoIP, self-configuring, autonomic networking
1	Diogo José Costa Alves, Edna Barros	A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.	SBCCI	2009	DBLP DOI BibTeX RDF	LBIST, compressed test patterns, test, SoC, self-test
1	Joni Jämsä, Mika Luimula, Pertti Verronen, Mika Pahkasalo, Juha Yli-Hemminki, Joni Heikkilä	Application of geosensor nodes in low-rate networks.	SenSys	2009	DBLP DOI BibTeX RDF	geospatial standards, location-awareness, geosensor networks
1	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
1	Yiorgos Sfikas, Yiorgos Tsiatouhas	Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing.	DDECS	2009	DBLP DOI BibTeX RDF
1	Kunal P. Ganeshpure, Sandip Kundu	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Ajit Pal, Santanu Chattopadhyay	Synthesis & Testing for Low Power.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	An Improved Soft-Error Rate Measurement Technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF