Search results for "test concurrency"

Found 14 publication records. Showing 14 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
1	Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang	IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Zhiyuan He, Zebo Peng, Petru Eles	Power constrained and defect-probability driven SoC test scheduling with test set partitioning.	DATE	2006	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	block-test scheduling, greedy algorithms, power constraints
1	Bai Hong Fang, Nicola Nicolici	Power-Constrained Embedded Memory BIST Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.	ITC	2003	DBLP DOI BibTeX RDF
1	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Power profile manipulation: a new approach for reducing test application time under power constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	V. Muresan, Xiaojun Wang, Mircea Vladutiu	A combined tree growing technique for block-test scheduling under power constraints.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Power-Constrained Block-Test List Scheduling. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	Block-Test Scheduling, Tree-Growing Technique, Power Dissipation, List Scheduling
1	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints.	VTS	2000	DBLP DOI BibTeX RDF
1	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Mahsa Vahidi, Alex Orailoglu	Metric-based transformations for self testable VLSI designs with high test concurrency.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Ian G. Harris, Alex Orailoglu	Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.	DAC	1994	DBLP DOI BibTeX RDF