Search results for "test generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
5	Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler	Deriving Signal Constraints to Accelerate Sequential Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3-valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table
5	Irith Pomeranz, Sudhakar M. Reddy	On improving genetic optimization based test generation.	ED&TC	1997	DBLP DOI BibTeX RDF	propagation Citation: I. Pomeranz, S.M. Reddy, On improving genetic optimization based test generation, edtc, pp.506, 1997 European Design and Test Conference (ED&TC '97), 1997 Peer Review Notice, Give Us Feedback Usage of this product signifies your acceptance of the Terms of Use. var addtoMethod=1, var AddURL = escape(http://doi.ieeecomputersociety.org/), var AddTitle = escape(On improving genetic optimization based test generation), Open Download Liferay.Portlet.onLoad({ canEditTitle: false, columnPos: 1, isStatic: 'end', namespacedId: 'p_p_id_digitallibraryabstract_WAR_plugins_INSTANCE_DjbO_', portletId: 'digitallibraryabstract_WAR_plugins_INSTANCE_DjbO' }), genetic algorithms, test generation, fault coverage, activation, benchmark circuit, crossover operator, genetic optimization
5	James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal	An asynchronous algorithm for sequential circuit test generation on a network of workstations.	VLSI Design	1995	DBLP DOI BibTeX RDF	fault list partitioning, multiple test generation processes, parallel algorithms, distributed algorithm, fault diagnosis, logic testing, sequential circuits, mathematical model, automatic test generation, automatic test software, workstation network, asynchronous algorithm, sequential circuit test generation
4	Matthew Kaplan, Tim Klinger, Amit M. Paradkar, Avik Sinha, Clay Williams, Cemal Yilmaz	Less is More: A Minimalistic Approach to UML Model-Based Conformance Test Generation.	ICST	2008	DBLP DOI BibTeX RDF	UML Model-based Test Generation, Use Case Based Test Generation, Test Verification Sequence, Fault Models for UML, Invariants analysis
4	Ana R. Cavalli, Stéphane Maag, Wissam Mallouli, Mikael Marche, Yves-Marie Quemener	Application of Two Test Generation Tools to an Industrial Case Study.	TestCom	2006	DBLP DOI BibTeX RDF	telephonic service, service testing, test generation tools, formal specification, conformance testing, Case study, automatic test generation, extended finite state machine
4	Suqin Tang, Cungen Cao	A Framework for Automated Test Generation in Intelligent Tutoring Systems.	KSEM	2006	DBLP DOI BibTeX RDF	domain conceptual model, testing goal, test-generation rules, individualized testing, test generation, Intelligent tutoring system
4	Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi	Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	diagnostic test generation, VLSI, test generation, fault
4	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
4	Rajesh Ramadoss, Michael L. Bushnell	Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults
4	Li-C. Wang, Magdy S. Abadir	Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	high-level test generation, assertion test generation, design validation, logic verification, symbolic trajectory evaluation
4	Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
4	Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	simulation-based test generation, distributed memory MIMD machines, shared memory MIMD machines, parallel search strategies, logic testing, fault coverage, NP-complete problems, VLSI circuits, parallel genetic algorithms, sequential circuit test generation
4	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
4	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
4	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
3	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
3	Milos Gligoric, Tihomir Gvero, Vilas Jagannath, Sarfraz Khurshid, Viktor Kuncak, Darko Marinov	Test generation through programming in UDITA.	ICSE	2010	DBLP DOI BibTeX RDF	Pex, UDITA, test filtering, test predicates, test generation, automated testing, test programs, Java PathFinder
3	Heon-Mo Koo, Prabhat Mishra	Functional test generation using design and property decomposition techniques.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	design decomposition, property decomposition, Model checking, test generation, pipelined processor, functional validation
3	Thao Dang, Tarik Nahhal	Coverage-guided test generation for continuous and hybrid systems.	Formal Methods in System Design	2009	DBLP DOI BibTeX RDF	Test generation, Hybrid systems, Model-based testing, Conformance testing, Test coverage
3	Bassem Elkarablieh, Patrice Godefroid, Michael Y. Levin	Precise pointer reasoning for dynamic test generation.	ISSTA	2009	DBLP DOI BibTeX RDF	pointer reasoning, software testing, program verification, automatic test generation
3	Irith Pomeranz, Sudhakar M. Reddy	State persistence: a property for guiding test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	broadside tests, test generation, transition faults, scan-based tests
3	Irith Pomeranz, Sudhakar M. Reddy	Partitioned n-detection test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
3	Irith Pomeranz, Sudhakar M. Reddy	Definition and application of approximate necessary assignments.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	necessary assignments, random test generation, test generation, stuck-at faults
3	Prabhat Mishra, Nikil Dutt	Specification-driven directed test generation for validation of pipelined processors.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Model checking, test generation, functional validation
3	Roberto Gómez, Alejandro Girón, Víctor H. Champac	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
3	Danilo Ravotto, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero	An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	Peripheral testing, ?GP3, test generation, approximate methods, evolutionary methods
3	Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita	Coverage-driven automatic test generation for uml activity diagrams.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	uml activity diagrams, test generation
3	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
3	Patrice Godefroid	Compositional dynamic test generation.	POPL	2007	DBLP DOI BibTeX RDF	compositional program analysis, scalability, software testing, program verification, automatic test generation
3	Clémentine Nebut, Franck Fleurey, Yves Le Traon, Jean-Marc Jézéquel	Automatic Test Generation: A Use Case Driven Approach.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	UML, test generation, scenarios, Use case, contracts
3	Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng	Simulation-Based Functional Test Generation for Embedded Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Simulation, learning, test generation, functional test
3	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	testability conditions, datapath testing, floating-point unit testing, Test generation, processor testing
3	Heon-Mo Koo, Prabhat Mishra	Test generation using SAT-based bounded model checking for validation of pipelined processors.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	test generation, functional validation
3	Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta	Test generation games from formal specifications.	DAC	2006	DBLP DOI BibTeX RDF	vacuity, test generation, realizability
3	Fabrice Bouquet, Frédéric Dadeau, Bruno Legeard	Automated Boundary Test Generation from JML Specifications.	FM	2006	DBLP DOI BibTeX RDF	boundary values, Test generation, automated, model-based, Java Modeling Language
3	Evan Martin	Automated test generation for access control policies.	OOPSLA Companion	2006	DBLP DOI BibTeX RDF	test generation, XACML, access control policy
3	Tamarah Arons, Elad Elster, Terry Murphy, Eli Singerman	Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation.	MTV	2006	DBLP DOI BibTeX RDF	Formal methods, Test generation, Software verification and validation
3	Kenneth J. Turner	Test generation for radiotherapy accelerators.	STTT	2005	DBLP DOI BibTeX RDF	Lotos (Language Of Temporal Ordering Specification), Test generation, Accelerator, Radiotherapy
3	Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara	An Effective Design for Hierarchical Test Generation Based on Strong Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Hierarchical test generation, strong testability, datapath, test plan
3	Changhai Nie, Baowen Xu, Liang Shi, Guowei Dong	Automatic Test Generation for N-Way Combinatorial Testing.	QoSA/SOQUA	2005	DBLP DOI BibTeX RDF	software testing, test generation, combinatorial testing
3	Achintya Halder, Abhijit Chatterjee	Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits.	ISQED	2004	DBLP DOI BibTeX RDF	test point selection, automated test generation, specification testing, parametric failure
3	Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov	Industrial experience with test generation languages for processor verification.	DAC	2004	DBLP DOI BibTeX RDF	test generation, functional verification, processor verification
3	Fabrice Bouquet, Bruno Legeard, Fabien Peureux, Eric Torreborre	Mastering Test Generation from Smart Card Software Formal Models.	CASSIS	2004	DBLP DOI BibTeX RDF	boundary testing, smart card standard, formal specifications, functional testing, Automated test generation
3	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri	A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	hierarchical test generation, constraint slicing, incremental slicing, program slicing, data-flow analysis
3	Fabrice Baray, Philippe Codognet, Daniel Diaz, Henri Michel	Code-Based Test Generation for Validation of Functional Processor Descriptions.	TACAS	2003	DBLP DOI BibTeX RDF	Code-based test generation, functional hardware verification, constraint solving techniques
3	Kuo-Chung Tai, Yu Lei	A Test Generation Strategy for Pairwise Testing.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	software testing, test generation, pairwise testing
3	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	time-based test generation, fault modeling, crosstalk, mixed-signal test
3	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	internally balanced structure, test generation, sequential circuit, combinational circuit, balanced structure
3	J. Jenny Li, W. Eric Wong	Automatic Test Generation from Communicating Extended Finite State Machine (CEFSM)-Based Models. (PDF / PS)	Symposium on Object-Oriented Real-Time Distributed Computing	2002	DBLP DOI BibTeX RDF	CEFSM, specification, test generation, SDL
3	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
3	Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick	Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	finite state machine with datapath, genetic algorithms, binary decision diagrams, automatic test generation
3	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira	RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	Defect-Oriented Test (DOT), low-energy test, test generation, RTL
3	Luay Ho Tahat, Atef Bader, Boris Vaysburg, Bogdan Korel	Requirement-Based Automated Black-Box Test Generation.	COMPSAC	2001	DBLP DOI BibTeX RDF	Selective Testing, Requirements, Regression Testing, System Model, SDL, Black-Box Testing, System Testing, Automated Test Generation, EFSM
3	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
3	Irith Pomeranz, Sudhakar M. Reddy	On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	minimal descriptions, test generation, Finite-state machines
3	Jian Shen, Jacob A. Abraham	An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	microprocessor design validation, coverage measurement, test generation
3	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
3	Sasikumar Cherubal, Abhijit Chatterjee	Test generation for fault isolation in analog circuits using behavioral models.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multiple parameter variations, manufacturing tolerances, test generation, fault location, behavioral models, analog circuits, analogue integrated circuits, fault isolation, circuit testing, behavioral descriptions, parametric failures, measurement noise
3	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
3	Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer	Test generation for crosstalk-induced faults: framework and computational result.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	2-vector test generation, crosstalk-induced faults, noise effects, design effort, debugging effort, pulses, signal speedup, signal slowdown, digital combinational circuits, mixed-signal test generator, XGEN, static values, dynamic signals, signal arrival times, rise times, fall times, integrated circuit testing, automatic test pattern generation, combinational circuits, accuracy, vectors, circuit analysis computing, crosstalk, transitions, integrated logic circuits, technology scaling, SPICE simulations, gate delay, circuit performance, timing information, clock frequency
3	Hideo Fujiwara	A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.	VLSI Design	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
3	Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
3	Irith Pomeranz, Sudhakar M. Reddy	On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	irredundant faults, built-in test generation, test generation, synchronous sequential circuits, Initial states
3	Irith Pomeranz, Sudhakar M. Reddy	Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	test generation, combinational circuits, stuck-at faults, logic simulation
3	Zhide Zeng, Jihua Chen, Pengxia Liu	A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Parallel Test Generation, Fault Parallelism, Fault Partitioning, Output Fan-in Cones, Input Fan-out Cones, Speed-up Ratio
3	Shiyi Xu, Tukwasibwe Justaf Frank	An Evaluation of Test Generation Algorithms for combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Genetic Algorithm, Test Generation, Forecasting, Testability
3	Jing-Jou Tang	An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Logic Threshold Voltage, test generation, fault modeling, fault simulation
3	Li Shen	Genetic Algorithm Based Test Generation for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential depth analysis, dynamic testability measure, genetic algorithm, test generation, Sequential testing
3	Dimitur Nikolaev Krustev	Software Test Generation Using Refinement Types. (PDF / PS)	ASE	1999	DBLP DOI BibTeX RDF	refinement types, process graphs, super-compilation, software testing, functional languages, automatic test generation
3	David Van Campenhout, Trevor N. Mudge, John P. Hayes	High-Level Test Generation for Design Verification of Pipelined Microprocessors.	DAC	1999	DBLP DOI BibTeX RDF	high-level test generation, pipelined microprocessors, sequential test generation, design verification
3	Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar	Fast Antirandom (FAR) Test Generation. (PDF / PS)	HASE	1998	DBLP DOI BibTeX RDF	Antirandom test generation, generation efficiency, test coverage
3	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	MIX: A Test Generation System for Synchronous Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits
3	Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.	DATE	1998	DBLP DOI BibTeX RDF	software testing, sequential circuits, automatic test generation, test sequence compaction
3	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	digital circuit testing, test generation, fault models, delay test, path delay faults
3	C. P. Ravikumar, Nitin Agrawal, Parul Agarwal	Hierarchical Delay Test Generation.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	delay test generation, path selection, hierarchical testing
3	Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita	An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, synchronous sequential circuit, Crosstalk fault
3	Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara	Sequential Test Generation Based on Circuit Pseudo-Transformation.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	acyclic structure, circuit pseudo-transformations, test generation, Sequential circuits, balanced structure
3	Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki	Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	DFT circuit, test generation, pass-transistor logic, stuck-on fault
3	Irith Pomeranz, Sudhakar M. Reddy	TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, finite-state machines, templates, synchronous sequential circuits
3	Ramesh C. Tekumalla, Premachandran R. Menon	Test generation for primitive path delay faults in combinational circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	Sensitizing cubes, static sensitizability, primitive faults, test generation
3	Christoph C. Michael, Gary McGraw, Michael Schatz, C. C. Walton	Genetic Algorithms for Dynamic Test Data Generation. (PDF / PS)	ASE	1997	DBLP DOI BibTeX RDF	program features, random test generation, genetic algorithms, genetic algorithms, software testing, combinatorial optimization, test generation, test data generation, test adequacy criteria
3	Kwang-Ting Cheng	Gate-level test generation for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	testing, automatic test generation, IC testing, sequential circuit test generation
3	Xinghao Chen, Michael L. Bushnell	Sequential circuit test generation using dynamic justification equivalence.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification
3	Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny	Optimization-based multifrequency test generation for analog circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	multifrequency test generation, tolerance effects, fault observability maximization, parametric faults
3	Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada	Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	supply current testing, D-frontier, test generation, IDDQ testing, PODEM
3	Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen	Invalid State Identification for Sequential Circuit Test Generation.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	invalid states, test generation, sequential circuits
3	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
3	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
3	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Automatic test generation using genetically-engineered distinguishing sequences.	VTS	1996	DBLP DOI BibTeX RDF	two-phase algorithm, fault effects, DIGATE, genetic algorithms, genetic algorithm, fault diagnosis, logic testing, sequential circuits, sequential circuit, automatic testing, sequences, flip-flops, automatic test generation, distinguishing sequence
3	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
3	Hideo Fujiwara, Tomoo Inoue	Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	distributed systems, parallel processing, test generation, Combinational circuits, fault simulation, granularity, client-server model
3	Kent L. Einspahr, Sharad C. Seth	A switch-level test generation system for synchronous and asynchronous circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
3	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
3	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
3	Elena Dubrova, Dilian Gurov, Jon C. Muzio	The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	full sensitivity evaluation, MVL circuits, functional level, m-valued n-variable functions, multi-valued logic circuits, fault diagnosis, logic testing, test generation, circuit analysis computing, multivalued logic circuits
3	Tomoo Inoue, Hironori Maeda, Hideo Fujiwara	A scheduling problem in test generation.	VTS	1995	DBLP DOI BibTeX RDF	test generation schedule, testing cost, dominating probability, ISCAS'85 benchmark circuits, combinational logic circuit testing, scheduling, logic testing, probability, integrated circuit testing, combinational circuits, automatic testing, test-pattern generation, processing time, scheduling problem
3	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
3	Anand Raghunathan, Pranav Ashar, Sharad Malik	Test generation for cyclic combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
3	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests