Search results for "test generation algorithms"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
2	Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara	A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.	DATE	2003	DBLP DOI BibTeX RDF
2	Shiyi Xu, Tukwasibwe Justaf Frank	An Evaluation of Test Generation Algorithms for combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Genetic Algorithm, Test Generation, Forecasting, Testability
2	Shiyi Xu, Gercy P. Dias	Testability forecasting for sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
2	Sreejit Chakravarty	A characterization of robust test-pairs for stuck-open faults.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	fault simulation, robust tests, stuck-open faults, test generation algorithms
1	Antti Nieminen, Antti Jääskeläinen, Heikki Virtanen, Mika Katara	A Comparison of Test Generation Algorithms for Testing Application Interactions.	QSIC	2011	DBLP DOI BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	Reduced complexity test generation algorithms for transition fault diagnosis.	ICCD	2011	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia	MERO: A Statistical Approach for Hardware Trojan Detection.	CHES	2009	DBLP DOI BibTeX RDF
1	Robert M. Hierons	Testing in the Distributed Test Architecture: An Extended Abstract.	QSIC	2008	DBLP DOI BibTeX RDF
1	Antti Jääskeläinen, Mika Katara, Antti Kervinen, Henri Heiskanen, Mika Maunumaa, Tuula Pääkkönen	Model-Based Testing Service on the Web.	TestCom/FATES	2008	DBLP DOI BibTeX RDF
1	Zoltán Pap, Mahadevan Subramaniam, Gábor Kovács, Gábor Árpád Németh	A Bounded Incremental Test Generation Algorithm for Finite State Machines.	TestCom/FATES	2007	DBLP DOI BibTeX RDF	finite state machine, conformance testing, incremental algorithms, test generation algorithms
1	Ziyuan Wang, Changhai Nie, Baowen Xu	Generating combinatorial test suite for interaction relationship.	SOQUA	2007	DBLP DOI BibTeX RDF	interaction relationship, software testing, test generation, combinatorial testing
1	Lars Frantzen, Jan Tretmans, Tim A. C. Willemse	A Symbolic Framework for Model-Based Testing.	FATES/RV	2006	DBLP DOI BibTeX RDF
1	Soumen Maity, Amiya Nayak	Improved Test Generation Algorithms for Pair-Wise Testing.	ISSRE	2005	DBLP DOI BibTeX RDF
1	Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li	Non-robust Test Generation for Crosstalk-Induced Delay Faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Moez Krichen, Stavros Tripakis	An Expressive and Implementable Formal Framework for Testing Real-Time Systems.	TestCom	2005	DBLP DOI BibTeX RDF
1	Valéry Tschaen	Test Generation Algorithms Based on Preorder Relations.	Model-Based Testing of Reactive Systems	2004	DBLP DOI BibTeX RDF
1	Ruibing Hao, David Lee, Rakesh K. Sinha, Nancy D. Griffeth	Integrated system interoperability testing with applications to VoIP.	IEEE/ACM Trans. Netw.	2004	DBLP DOI BibTeX RDF	redundancy, TCP/IP, coverage, VoIP, integrated system, interoperability testing
1	Toshiaki Shiba, Tatsuhiro Tsuchiya, Tohru Kikuno	Using Artificial Life Techniques to Generate Test Cases for Combinatorial Testing.	COMPSAC	2004	DBLP DOI BibTeX RDF
1		Part II. Testing of Labeled Transition Systems.	Model-Based Testing of Reactive Systems	2004	DBLP DOI BibTeX RDF
1	Tuomo Pyhälä, Keijo Heljanko	Specification Coverage Aided Test Selection.	ACSD	2003	DBLP DOI BibTeX RDF
1	Hyoung Seok Hong, Sung Deok Cha, Insup Lee, Oleg Sokolsky, Hasan Ural	Data Flow Testing as Model Checking. (PDF / PS)	ICSE	2003	DBLP DOI BibTeX RDF
1	Alfredo Ferro, Rosalba Giugno, Alfredo Pulvirenti	Efficient Boundary Values Generation in General Metric Spaces for Software Component Testing.	Verification: Theory and Practice	2003	DBLP DOI BibTeX RDF
1	Biranchinath Sahu, Abhijit Chatterjee	Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	test transfer function model, AC testing, optimization, fault simulation
1	Emil Gizdarski, Hideo Fujiwara	SPIRIT: A Highly Robust Combinational Test Generation Algorithm.	VTS	2001	DBLP DOI BibTeX RDF
1	Shiyi Xu, Tukwasibwe Justaf Frank	Forecasting the Efficiency of Test Generation Algorithms for Combinational Circuits.	J. Comput. Sci. Technol.	2000	DBLP DOI BibTeX RDF
1	René G. de Vries, Jan Tretmans	On-the-fly Conformance Testing using SPIN.	STTT	2000	DBLP DOI BibTeX RDF	Spin verification tool, Formal methods, Conformance testing, Test automation, Test generation algorithms
1	Shamim Begum, Meeta Sharma, Ahmed Helmy, Sandeep K. S. Gupta	Systematic Testing of Protocol Robustness: Case Studies on Mobile IP and MARS. (PDF / PS)	LCN	2000	DBLP DOI BibTeX RDF	systematic testing of robustness by evaluation of synthesized scenarios, registration message, MARS server, forward search, multicast address resolution server protocol, protocol robustness, Internet, performance, mobile computing, complexity, protocols, asynchronous transfer mode, ATM, topologies, network topology, error, mobile IP, search problems, multicast communication, STRESS, IP-multicast, network servers, packet radio networks, MIP, MARS, event sequences, land mobile radio, test generation algorithm, home agent, asymptotic complexity
1	Ed Brinksma, Jan Tretmans	Testing Transition Systems: An Annotated Bibliography.	MOVEP	2000	DBLP DOI BibTeX RDF
1	Jian Shen, Jacob A. Abraham	Verification of Processor Microarchitectures.	VTS	1999	DBLP DOI BibTeX RDF
1	Yu Lei, Kuo-Chung Tai	In-Parameter-Order: A Test Generation Strategy for Pairwise Testing. (PDF / PS)	HASE	1998	DBLP DOI BibTeX RDF
1	S. Bose, P. Agrawal, V. D. Agrawal	A rated-clock test method for path delay faults.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Bapiraju Vinnakota, Jason Andrews	Fast fault translation.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi	Testability Prediction for Sequential Circuits Using Neural Network.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
1	Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler	Deriving Signal Constraints to Accelerate Sequential Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3-valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table
1	Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal	Redundancy removal and test generation for circuits with non-Boolean primitives.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Y.-M. Hur, J.-H. Shin, K.-H. Lee, Y.-S. Son, I.-C. Lim, Y.-H. Kim	Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
1	Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Combinational test generation using satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Mahesh A. Iyer, Miron Abramovici	FIRE: a fault-independent combinational redundancy identification algorithm.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
1	Srimat T. Chakradhar, Steven G. Rothweiler	Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives.	VTS	1995	DBLP DOI BibTeX RDF
1	Ted Stanion, Debashis Bhattacharya, Carl Sechen	An efficient method for generating exhaustive test sets.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Kwang-Ting Cheng, Hi-Keung Tony Ma	On the over-specification problem in sequential ATPG algorithms.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
1	Chun-Hung Chen, Jacob A. Abraham	High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms.	ITC	1991	DBLP DOI BibTeX RDF
1	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential Test Generation at the Register-Transfer and Logic Levels.	DAC	1990	DBLP DOI BibTeX RDF
1	Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann	A graphical system for hierarchical specifications and checkups of VLSI circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton	Redundancies and don't cares in sequential logic synthesis.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	redundancies, synthesis for testability, don't cares
1	Hyoung B. Min, William A. Rogers	Search strategy switching: A cost model and an analysis of backtracking.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	search strategy switching, ATPG, fault coverage, backtracking
1	Sunil K. Jain, Vishwani D. Agrawal	Modeling and Test Generation Algorithms for MOS Circuits.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF
1	Andrew V. Goldberg, Karl J. Lieberherr	Efficient Test Generation Algorithms.	ITC	1985	DBLP BibTeX RDF
1	Hideo Fujiwara, Takeshi Shimono	On the Acceleration of Test Generation Algorithms.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults
1	Ytzhak H. Levendel, Premachandran R. Menon	Test Generation Algorithms for Computer Hardware Description Languages.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF