Search results for "test power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Reducing Average and Peak Test Power Through Scan Chain Modification.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	test power reduction, scan chain modification, average test power, peak test power, scan testing
3	Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara	Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Scan forest, test application cost, test data volume, test power
3	Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov	A retention-aware test power model for embedded SRAM.	ASP-DAC	2005	DBLP DOI BibTeX RDF	data retention fault test, multiple embedded SRAMs, test power modeling, test scheduling
3	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Test Power: a Big Issue in Large SOC Designs.	DELTA	2002	DBLP DOI BibTeX RDF	DfT, BIST, Scan, Low Power Testing, Test Power
2	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
2	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
2	Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
2	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
2	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
2	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	A critical-path-aware partial gating approach for test power reduction.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan testing
2	Xiaoding Chen, Michael S. Hsiao	An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
2	X.-L. Huang, J.-L. Huang	A routability constrained scan chain ordering technique for test power reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard	Minimizing test power in SRAM through reduction of pre-charge activity.	DATE	2006	DBLP DOI BibTeX RDF
2	Ozgur Sinanoglu, Alex Orailoglu	Test power reductions through computationally efficient, decoupled scan chain modifications.	IEEE Transactions on Reliability	2005	DBLP DOI BibTeX RDF
2	Dong Hyun Baik, Kewal K. Saluja	State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara	Random Access Scan: A solution to test power, test data volume and test time.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Ozgur Sinanoglu, Alex Orailoglu	Modeling Scan Chain Modifications For Scan-in Test Power Minimization.	ITC	2003	DBLP DOI BibTeX RDF
2	Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu	A cost-effective scan architecture for scan testing with non-scan test power and test application cost.	DAC	2003	DBLP DOI BibTeX RDF
2	Ozgur Sinanoglu, Alex Orailoglu	Aggressive Test Power Reduction Through Test Stimuli Transformation.	ICCD	2003	DBLP DOI BibTeX RDF
2	Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min	Test Power Optimization Techniques for CMOS Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Test Power Reduction through Minimization of Scan Chain Transitions.	VTS	2002	DBLP DOI BibTeX RDF
2	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
1	Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu	Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu	Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	At-speed delay fault testing, Power-aware Testing, Functional power
1	Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui	Reducing Test Power for Embedded Memories.	DFT	2011	DBLP DOI BibTeX RDF
1	Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya	PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Chia-Yi Lin, Li-Chung Hsu, Hung-Ming Chen	On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Jun Liu, Yinhe Han, Xiaowei Li	Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin	Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.	IET Computers & Digital Techniques	2010	DBLP DOI BibTeX RDF
1	Chia-Yi Lin, Hsiu-Chuan Lin, Hung-Ming Chen	On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed	Is test power reduction through X-filling good enough?	ITC	2010	DBLP DOI BibTeX RDF
1	Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe	Methodology for early and accurate test power estimation at RTL.	ITC	2010	DBLP DOI BibTeX RDF
1	S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay	Customizing pattern set for test power reduction via improved X-identification and reordering.	ISLPED	2010	DBLP DOI BibTeX RDF	don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power
1	Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara	Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah	Test power reduction in compression-based reconfigurable scan architectures.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Zhen Chen, Sharad C. Seth, Dong Xiang	A novel hybrid delay testing scheme with low test power, volume, and time.	VTS	2010	DBLP DOI BibTeX RDF
1	Mokhtar Hirech	Test cost and test power conflicts: EDA perspective.	VTS	2010	DBLP DOI BibTeX RDF
1	Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya	A Unified Solution to Scan Test Volume, Time, and Power Minimization.	VLSI Design	2010	DBLP DOI BibTeX RDF	Test power minimization, Test time reduction, Test data reduction, Nonlinear scan
1	George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	José M. Solana	Reducing test application time, test data volume and test power through Virtual Chain Partition.	Integration	2009	DBLP DOI BibTeX RDF
1	C. V. Gayathri, N. Kayalvizhi, M. Mallikadevi	Generation of New March Tests with Low Test Power and High Fault Coverage by Test Sequence Reordering Using Genetic Algorithm.	ARTCom	2009	DBLP DOI BibTeX RDF
1	Jun Liu, Yinhe Han, Xiaowei Li	Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Oana Pop, Doru Paunescu, Stefan Kilyeni, Mircea Nemes, Annamaria Kilyeni, Constantin Barbulescu	Probabilistic distribution factors assessment using OptimalPowerPrice Mathematica software, case study: Test 25 buses test power system.	SACI	2009	DBLP DOI BibTeX RDF
1	Bin Zhou, Yizheng Ye, Xin-chun Wu, Zhao-lin Li	Reduction of Test Power and Data Volume in BIST Scheme based on Scan Slice Overlapping.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Jun Xu, Xiangku Li	Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs.	NAS	2009	DBLP DOI BibTeX RDF
1	Zhen Chen, Dong Xiang, Boxue Yin	A power-effective scan architecture using scan flip-flops clustering and post-generation filling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
1	Ajit Pal, Santanu Chattopadhyay	Synthesis & Testing for Low Power.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Ozgur Sinanoglu	Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Ivano Midulla, Chouki Aktouf	Test Power Analysis at Register Transfer Level.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti	A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	DongSup Song, Jin-Ho Ahn, Taejin Kim, Sungho Kang	MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Vishwani D. Agrawal	A tutorial on test power.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Jarad Niemi, Meredith Smith, David Banks	Test Power for Drug Abuse Surveillance.	BioSecure	2008	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
1	David R. Bild, Sanchit Misra, Thidapat Chantem, Prabhat Kumar, Robert P. Dick, Xiaobo Sharon Hu, Li Shang, Alok N. Choudhary	Temperature-aware test scheduling for multiprocessor systems-on-chip.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu	On capture power-aware test data compression for scan-based testing.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Power-aware SoC test planning for effective utilization of port-scalable testers.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	port-scalable testers, test access architecture, integer linear programming, SoC test
1	Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara	Localized random access scan: Towards low area and routing overhead.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Erik Jan Marinissen	Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.	DATE	2008	DBLP DOI BibTeX RDF
1	Bei Cao, Liyi Xiao, Yongsheng Wang	A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.	DELTA	2008	DBLP DOI BibTeX RDF
1	Yong-sheng Cheng, Zhiqiang You, Jishun Kuang	Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.	DELTA	2008	DBLP DOI BibTeX RDF	full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
1	Jia Li, Qiang Xu, Yu Hu, Xiaowei Li	Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.	DELTA	2008	DBLP DOI BibTeX RDF	NoC channel utilization, test wrapper, interleaved test scheduling
1	Tian Chen, Huaguo Liang, Minsheng Zhang, Wei Wang	A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi	An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Praveen Bhojwani, Rabi N. Mahapatra	Robust Concurrent Online Testing of Network-on-Chip-Based SoCs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Axel Schneider, Holk Cruse, Josef Schmitz	Winching up heavy loads with a compliant arm: a new local joint controller.	Biological Cybernetics	2008	DBLP DOI BibTeX RDF	Joint coordination, Turning a crank, Positive feedback, Compliant motion, Active compliance, Equilibrium point hypothesis, Decentralized control, Contour tracking
1	Hong-Sik Kim, Sungho Kang, Michael S. Hsiao	A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Keyword System on a chip, Test compression, Low power testing, Scan testing
1	Erik Larsson, Zebo Peng	A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Core wrapper, Test scheduling, Preemption, Power constraint
1	Da Wang, Yu Hu, Huawei Li, Xiaowei Li	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
1	K. Paramasivam, K. Gunavathi	Reordering Algorithm for Minimizing Test Power in VLSI Circuits.	Engineering Letters	2007	DBLP BibTeX RDF
1	Qiang Xu, Dianwei Hu, Dong Xiang	Pattern-directed circuit virtual partitioning for test power reduction.	ITC	2007	DBLP DOI BibTeX RDF
1	Mehdi Kamal, Somayyeh Koohi, Shaahin Hessabi	Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs.	DFT	2007	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi	Using the inter- and intra-switch regularity in NoC switch testing.	DATE	2007	DBLP DOI BibTeX RDF
1	Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara	Efficient path delay test generation based on stuck-at test generation using checker circuitry.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Chia-Yi Lin, Hung-Ming Chen	A selective pattern-compression scheme for power and test-data reduction.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	J. Tang, J. Langston, M. Sloderbeck, D. Ouellette, P. G. McLaren	In system emulation (ISE) of a current differential back-up protection relay.	SCSC	2007	DBLP DOI BibTeX RDF	differential protection, wide-area back-up protection, emulation, relay
1	Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara	Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Praveen Bhojwani, Rabi N. Mahapatra	An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Wang-Dauh Tseng, Lung-Jen Lee	Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.	MTV	2007	DBLP DOI BibTeX RDF
1	Kim T. Le, Dong Hyun Baik, Kewal K. Saluja	Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda	Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jinkyu Lee, Nur A. Touba	LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yuh-Jye Lee, Su-Yun Huang	Reduced Support Vector Machines: A Statistical Theory.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	S.-P. Lin, C.-L. Lee, J.-E. Chen, J.-J. Chen, K.-L. Luo, W.-C. Wu	A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu	Low Cost Scan Test by Test Correlation Utilization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	test correlation, scan architecture design, test data compression, scan-based testing
1	Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
1	Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.	ITC	2006	DBLP DOI BibTeX RDF
1	Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu	A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez	Testing and Diagnosis of Power Switches in SOCs.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi	Enhancing Delay Fault Coverage through Low Power Segmented Scan.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Li-Chung Hsu, Hung-Ming Chen	On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design.	ISQED	2006	DBLP DOI BibTeX RDF