Search results for "test synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Soheil Aminzadeh, Saeed Safari	Co-evolutionary high-level test synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	co-evolutionary algorithm, module binding, genetic algorithm, scheduling, register allocation, high-level test synthesis
3	Frank F. Hsu, Janak H. Patel	High-Level Controllability and Observability Analysis for Test Synthesis.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	controllability, observability, high-level test synthesis, behavioral modification
3	Christos A. Papachristou, Mikhail Baklashov, Kowen Lai	High-Level Test Synthesis for Behavioral and Structural Designs.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	built-in self test, DFT, test synthesis
3	Kowen Lai, Christos A. Papachristou, Mikhail Baklashov	BIST testability enhancement using high level test synthesis for behavioral and structural designs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis
3	Christos A. Papachristou, Mikhail Baklashov	A test synthesis technique using redundant register transfers.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions
2	Simon Pickin, Claude Jard, Thierry Jéron, Jean-Marc Jézéquel, Yves Le Traon	Test Synthesis from UML Models of Distributed Software.	IEEE Trans. Software Eng.	2007	DBLP DOI BibTeX RDF	Formal methods, testing tools, object-oriented design methods
2	Sying-Jyan Wang, Tung-Hua Yeh	High-level test synthesis for delay fault testability.	DATE	2007	DBLP DOI BibTeX RDF
2	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
2	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.	DSD	2004	DBLP DOI BibTeX RDF	BIST insertion, wiring area, test synthesis
2	Nicola Nicolici, Bashir M. Al-Hashimi	Power-Conscious Test Synthesis and Scheduling.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	Simon Pickin, Claude Jard, Yves Le Traon, Thierry Jéron, Jean-Marc Jézéquel, Alain Le Guennec	System Test Synthesis from UML Models of Distributed Software.	FORTE	2002	DBLP DOI BibTeX RDF
2	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	VLIW processor test, test-time analysis, Design for Testability (DfT), test synthesis
2	Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu	Test Synthesis for Mixed-Signal SOC Paths.	DATE	2000	DBLP DOI BibTeX RDF
2	Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken	Manufacturability and Testability Oriented Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
2	Yiorgos Makris, Alex Orailoglu	Channel-Based Behavioral Test Synthesis for Improved Module Reachability.	DATE	1999	DBLP DOI BibTeX RDF
2	Laurence Tianruo Yang, Zebo Peng	Incremental Testability Analysis for Partial Scan Selection and Design Transformations.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	incremental testability analysis, partial scan selection, design transformation, register transfer level, high-level test synthesis
2	Laurence Tianruo Yang, Zebo Peng	An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis.	DATE	1998	DBLP DOI BibTeX RDF
2	Kelly A. Ockunzzi, Christos A. Papachristou	Testability Enhancement for Control-Flow Intensive Behaviors.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	behavioral testability analysis and insertion, BIST, test synthesis
2	Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng	A Test Synthesis Approach to Reducing BALLAST DFT Overhead.	DAC	1997	DBLP DOI BibTeX RDF
2	Joan Carletta, Christos A. Papachristou	Behavioral Testability Insertion for Datapath/Controller Circuits.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	behavioral testability analysis, BIST, test synthesis
2	Marcel Jacomet, Walter Guggenbühl	Layout-dependent fault analysis and test synthesis for CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Tung-Hua Yeh, Sying-Jyan Wang	Thermal Safe High Level Test Synthesis for Hierarchical Testability.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Tung-Hua Yeh	High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
1	Ali Pourghaffari bashari, Saadat Pourmozafari	A Graph-based Framework for High-level Test Synthesis.	World Congress on Engineering	2007	DBLP BibTeX RDF
1	Jacques Klein, Franck Fleurey, Jean-Marc Jézéquel	Weaving Multiple Aspects in Sequence Diagrams.	T. Aspect-Oriented Software Development	2007	DBLP DOI BibTeX RDF
1	Petros Oikonomakos, Mark Zwolinski	An Integrated High-Level On-Line Test Synthesis Tool.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh	A parameterized graph-based framework for high-level test synthesis.	Integration	2006	DBLP DOI BibTeX RDF
1	Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara	Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	BIST insertion, wiring area, simulated annealing, test synthesis
1	C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar	A Framework for Distributed and Hierarchical Design-for-Test.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
1	Claude Jard, Thierry Jéron	TGV: theory, principles and algorithms.	STTT	2005	DBLP DOI BibTeX RDF	Test generation/synthesis, Model-checking, Protocols, Reactive systems, Conformance testing, Transition systems
1	Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara	Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	M. S. Gaur, Mark Zwolinski	Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Laurence Tianruo Yang, Jon C. Muzio	Testing Methodologies for Embedded Systems and Systems-on-Chip.	ICESS	2004	DBLP DOI BibTeX RDF
1	Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara	Test Synthesis for Datapaths Using Datapath-Controller Functions.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit
1	Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir	A novel improvement technique for high-level test synthesis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Niraj K. Jha	Test synthesis of systems-on-a-chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Claude Jard	Principles of Distributed Test Synthesis based on True-concurrency Models.	TestCom	2002	DBLP BibTeX RDF
1	Christoph Hoffmann	A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits.	DATE	2002	DBLP DOI BibTeX RDF
1	Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur	Integrating DFT in the Physical Synthesis Flow.	ITC	2002	DBLP DOI BibTeX RDF
1	Kelly A. Ockunzzi, Christos A. Papachristou	Breaking Correlation to Improve Testability.	VTS	2001	DBLP DOI BibTeX RDF	BIST, DFT, Test Synthesis
1	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	BIST, datapath, high level test synthesis
1	Srivaths Ravi, Niraj K. Jha	Synthesis of System-on-a-chip for Testability.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane	System-on-Chip Testability Using LSSD Scan Structures.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Bashir M. Al-Hashimi	Power conscious test synthesis and scheduling for BIST RTL data paths.	ITC	2000	DBLP DOI BibTeX RDF
1	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	BISTing Datapaths under Heterogeneous Test Schemes.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	RT level, BIST, datapath, test synthesis
1	Kamran Zarrineh, Shambhu J. Upadhyaya	A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units.	VTS	1999	DBLP DOI BibTeX RDF
1	Indradeep Ghosh, Niraj K. Jha	High-level test synthesis: a survey.	Integration	1998	DBLP DOI BibTeX RDF
1	Michiko Inoue, Hideo Fujiwara	An approach to test synthesis from higher level.	Integration	1998	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
1	Jian Shen, Jacob A. Abraham	Synthesis of Native Mode Self-Test Programs.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	native mode self-test, test synthesis, functional test generation
1	Cheng-Wen Wu, Chih-Yuang Su	A Probabilistic Model for Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
1	Vivek Chickermane, Kamran Zarrineh	Addressing Early Design-For-Test Synthesis in a Production Environment.	ITC	1997	DBLP DOI BibTeX RDF
1	Christian Dufaza, Hassan Ihs	Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits.	VTS	1997	DBLP DOI BibTeX RDF
1	Hassan Ihs, Christian Dufaza	Test synthesis for DC test of switched-capacitors circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Kowen Lai, Christos A. Papachristou, Mikhail Baklashov	High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains.	ICCD	1997	DBLP BibTeX RDF
1	Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta	An RTL methodology to enable low overhead combinational testing.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Mehrdad Nourani, Christos A. Papachristou	Structural BIST insertion using behavioral test analysis.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Raimund Ubar	Test Synthesis with Alternative Graphs.	IEEE Design & Test of Computers	1996	DBLP DOI BibTeX RDF
1	Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer	A Design For Test Perspective on I/O Management. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	I/O pads, High Level Synthesis, Design For Test, Boundary Scan
1	Mitsuteru Yukishita, Kiyoshi Oguri, Tsukasa Kawaoka	Test Synthesis from Behavioral Description Based on Data Transfer Analysis.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Robert C. Aitken	An Overview of Test Synthesis Tools.	IEEE Design & Test of Computers	1995	DBLP DOI BibTeX RDF
1	Christos A. Papachristou, Joan Carletta	Test Synthesis in the Behavioral Domain.	ITC	1995	DBLP DOI BibTeX RDF
1	Peter C. Maxwell	The Many Faces of Test Synthesis.	ITC	1995	DBLP DOI BibTeX RDF
1	Rabindra K. Roy	Advantages of High-Level Test Synthesis over Design for Test.	ITC	1995	DBLP DOI BibTeX RDF
1	Kamalesh N. Ruparel	Test Synthesis: From Wishful Thinking to Reality.	ITC	1995	DBLP DOI BibTeX RDF
1	Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre	Is High-Level Test Synthesis Just Design for Test?	ITC	1995	DBLP DOI BibTeX RDF
1	Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich	Pattern generation for a deterministic BIST scheme.	ICCAD	1995	DBLP DOI BibTeX RDF	ATPG, BIST, Test Synthesis
1	Oliver F. Haberl, Thomas Kropf	HIST: A hierarchical self test methodology for chips, boards, and systems.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	Boundary-scan architecture, hierarchical self test, self test synthesis, built-in self test (BIST), system test
1	Henry Cox	Synthesizing Circuits with Implicit Testability Constraints.	IEEE Design & Test of Computers	1995	DBLP DOI BibTeX RDF
1	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Raimund Ubar	Test Generation for Digital Systems Based on Alternative Graphs.	EDCC	1994	DBLP DOI BibTeX RDF
1	Gunnar Carlsson	Test Synthesis from a User Perspective.	ITC	1993	DBLP BibTeX RDF
1	Andrzej Krasniewski	Design for verification testability.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Philip Kaszerman	A Geometric Test-Synthesis Procedure for a Threshold Device	Information and Control	1963	DBLP DOI BibTeX RDF