Search results for "test-per-clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
3	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding
3	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Test-per-Clock Schemes, Reseeding Techniques, Built-In Self-Test, Linear Feedback Shift Registers, Test Pattern Generation
2	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
2	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
2	Ondrej Novák, Jiri Nosek	Test-per-Clock Testing of the Circuits with Scan.	IOLTW	2001	DBLP DOI BibTeX RDF
2	Shivakumar Swaminathan, Krishnendu Chakrabarty	On Using Twisted-Ring Counters for Test Set Embedding in BIST.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
2	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
1	Dimitris Magos, Ioannis Voyiatzis, Steffen Tarnick	An Accumulator - Based Test-Per-Clock Scheme.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Effective BIST for crosstalk faults in interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	An Improved Soft-Error Rate Measurement Technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Bin Zhou, Yizheng Ye, Yongsheng Wang	Simultaneous reduction in test data volume and test time for TRC-reseeding.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	encoded vector, twisted-ring counter, built-in self test
1	Petr Fiser	Pseudo-Random Pattern Generator Design for Column-Matching BIST.	DSD	2007	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	Accelerating Soft Error Rate Testing Through Pattern Selection.	IOLTS	2007	DBLP DOI BibTeX RDF	soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error
1	Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Test-per-Clock Detection, Localization and Identification of Interconnect Faults.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
1	M. Shah, D. Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles	Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.	DSD	2005	DBLP DOI BibTeX RDF
1	Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos	Reseeding-Based Test Set Embedding with Reduced Test Sequences.	ISQED	2005	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS	2003	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
1	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
1	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas	A new built-in TPG method for circuits with random patternresistant faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Power profile manipulation: a new approach for reducing test application time under power constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Nur A. Touba	Circular BIST with state skipping.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara	BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	RTL data path, single-control testability, built-in self-test, design for testability, concurrent test, hierarchical test
1	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
1	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
1	Abhijit Jas, Kartik Mohanram, Nur A. Touba	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
1	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	design-for-testability, BIST, scan design
1	Albrecht P. Stroele, Hans-Joachim Wunderlich	Hardware-optimal test register insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Debaditya Mukherjee, Melvin A. Breuer	An IEEE 1149.1 Compliant Test Control Architecture.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	test control, local test control, distributed test control, dynamic test control, built-in self-test, design-for-test, boundary scan, test bus
1	Danial J. Neebel, Charles R. Kime	Cellular Automata for Weighted Random Pattern Generation.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	multiple weight sets, hybrid cellular automata, weighted cellular automata, test-per-clock pattern generation, Built-in self-test, cellular automata, weighted random patterns
1	Albrecht P. Stroele, Hans-Joachim Wunderlich	Test register insertion with minimum hardware cost.	ICCAD	1995	DBLP DOI BibTeX RDF	test register insertion, BILBO, CBILBO, Built-in self-test