Search results for "test-per-scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.	IOLTS	2006	DBLP DOI BibTeX RDF	Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
3	Xiaodong Zhang, Kaushik Roy	Power Reduction in Test-Per-Scan BIST.	IOLTW	2000	DBLP DOI BibTeX RDF	Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
2	Seongmoon Wang, Sandeep K. Gupta	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
2	Nitin Parimi, Xiaoling Sun	Toggle-Masking for Test-per-Scan VLSI Circuits.	DFT	2004	DBLP DOI BibTeX RDF
1	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
1	Snehal Udar, Dimitri Kagaris	LFSR Reseeding with Irreducible Polynomials.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
1	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
1	M. Shah, D. Nagchoudhuri	BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles	Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.	DSD	2005	DBLP DOI BibTeX RDF
1	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos	Accumulator based Test-per-Scan BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu	Scan-Based BIST Using an Improved Scan Forest Architecture.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy	A Technique to Reduce Power and Test Application Time in BIST.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
1	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS	2003	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
1	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Power profile manipulation: a new approach for reducing test application time under power constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
1	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
1	Seongmoon Wang, Sandeep K. Gupta	LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.	ITC	1999	DBLP DOI BibTeX RDF