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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 28 occurrences of 27 keywords
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Results
Found 5 publication records. Showing 5 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Shiyi Xu, Wei Cen |
Forecasting the efficiency of test generation algorithms for digital circuits.  |
Asian Test Symposium  |
2000 |
DBLP DOI BibTeX RDF |
efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms |
| 2 | Hiroaki Ueda, Kozo Kinoshita |
Low power design and its testability.  |
Asian Test Symposium  |
1995 |
DBLP DOI BibTeX RDF |
power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability |
| 1 | Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes |
Signature-Based SER Analysis and Design of Logic Circuits.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir |
A novel improvement technique for high-level test synthesis.  |
ISCAS  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi |
Testability Prediction for Sequential Circuits Using Neural Network.  |
Asian Test Symposium  |
1997 |
DBLP DOI BibTeX RDF |
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