Search results for "testing time"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Il-soo Lee, Tony Ambler	Two efficient methods to reduce power and testing time.	ISLPED	2005	DBLP DOI BibTeX RDF	reordering scan latches, scan architecture, power, testing time
2	Ossi Taipale, Heikki Kälviäinen, Kari Smolander	Factors Affecting Software Testing Time Schedule.	ASWEC	2006	DBLP DOI BibTeX RDF	communication and interaction, software testing, software process improvement, regression analysis
2	Anshuman Chandra, Krishnendu Chakrabarty	Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, system-on-a-chip testing, test set encoding, variable-to-variable-length codes, automatic test equipment (ATE), testing time, embedded core testing
2	Anshuman Chandra, Krishnendu Chakrabarty	A unified approach to reduce SOC test data volume, scan power and testing time.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Vikram Iyengar, Krishnendu Chakrabarty	Test Bus Sizing for System-on-a-Chip.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Core-based systems, integer linear programming, linearization, test access mechanism (TAM), testing time, embedded core testing, test bus
2	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	test wrapper, integer linear programming, test access mechanism (TAM), testing time, Embedded core testing
2	Zahra Sadat Ebadi, André Ivanov	Design of an Optimal Test Access Architecture Using a Genetic Algorithm.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	Optimal testing time, test data width, Genetic Algorithm, Test Access Mechanism (TAM), SOC testing, Embedded core testing
2	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
2	Makoto Sugihara, Hiroshi Date, Hiroto Yasuura	A novel test methodology for core-based system LSIs and a testing time minimization problem.	ITC	1998	DBLP DOI BibTeX RDF
2	Cheng-Wen Wu	On energy efficiency of VLSI testing.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test efficiency models, CMOS power consumption model, high testability, high power dissipation, high-power testing, transition activity factor, fabricated chip, testing energy, VLSI, energy efficiency, fault coverage, design optimization, VLSI testing, testing time, test efficiency, testing power
2	Chen-Yang Pan, Kwang-Ting Cheng	Implicit functional testing for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response
2	Sandeep Pagey	Fast functional testing of delay-insensitive circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	four-phase handshake signalling, Martin's method, distributed circuit, OR/C blocks, generation of test sequences, program flow graph, logic testing, delays, design for testability, logic CAD, asynchronous circuits, functional testing, testing time, self-timed circuits, delay-insensitive circuits, OR gates
2	J. A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
1	Pradeep Kumar, Yogesh Singh	Assessment of software testing time using soft computing techniques.	ACM SIGSOFT Software Engineering Notes	2012	DBLP DOI BibTeX RDF
1	J. A. Pérez-Benitez, L. R. Padovese	Falling sheet envelope method for non-destructive testing time-dependent signals.	Expert Syst. Appl.	2011	DBLP DOI BibTeX RDF
1	Tomohiko Ogawa, Haruo Kobayashi, Satoshi Uemori, Yohei Tan, Satoshi Ito, Nobukazu Takai, Takahiro J. Yamaguchi, Kiichi Niitsu	Design for Testability That Reduces Linearity Testing Time of SAR ADCs.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Roberto Pietrantuono, Stefano Russo, Kishor S. Trivedi	Software Reliability and Testing Time Allocation: An Architecture-Based Approach.	IEEE Trans. Software Eng.	2010	DBLP DOI BibTeX RDF	Reliability, software architecture, software testing
1	Robert W. Day, Matthew D. Dean, Robert S. Garfinkel, Steven M. Thompson	Improving patient flow in a hospital through dynamic allocation of cardiac diagnostic testing time slots.	Decision Support Systems	2010	DBLP DOI BibTeX RDF
1	P. K. Kapur, Anu G. Aggarwal, Gurjeet Kaur	Simultaneous allocation of testing time and resources for a modular software.	Int. J. Systems Assurance Engineering and Management	2010	DBLP DOI BibTeX RDF
1	Gregory Neven	Privacy-enhanced access control in primelife.	Digital Identity Management	2010	DBLP DOI BibTeX RDF
1	Joe Tang, Eric Lo	A lightweight framework for testing database applications.	SAC	2010	DBLP DOI BibTeX RDF	symbolic database, symbolic query processing, testing, database, query processing, symbolic execution
1	Amir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum	Pseudorandom Stimuli Generation for Testing Time-to-Digital Converters on an FPGA.	IEEE T. Instrumentation and Measurement	2009	DBLP DOI BibTeX RDF
1	Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng	Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC.	VTS	2009	DBLP DOI BibTeX RDF
1	Xiuli Ma, Guoqiang Mu, Xiaoqing Yu	Kernel-based immunity synergetic network for image classification.	GEC Summit	2009	DBLP DOI BibTeX RDF	image classification., immunity clonal algorithm, synergetic neural network, kernel learning
1	Sandro Fouché, Myra B. Cohen, Adam A. Porter	Incremental covering array failure characterization in large configuration spaces.	ISSTA	2009	DBLP DOI BibTeX RDF	testing, distributed testing
1	Ehud Trainin, Yarden Nir-Buchbinder, Rachel Tzoref-Brill, Aviad Zlotnick, Shmuel Ur, Eitan Farchi	Forcing small models of conditions on program interleaving for detection of concurrent bugs.	PADTAD	2009	DBLP DOI BibTeX RDF	concurrency bug patterns, dynamic exploration, forcing algorithm, model of conditions on program interleaving, analysis
1	José Iria	Automating knowledge capture in the aerospace domain.	K-CAP	2009	DBLP DOI BibTeX RDF	machine learning, information extraction, knowledge capture, aerospace
1	Hu Guan, Jingyu Zhou, Minyi Guo	A class-feature-centroid classifier for text categorization.	WWW	2009	DBLP DOI BibTeX RDF	denormalized cosine measure, inner-class, inter-class, text classification, centroid
1	Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
1	Daniel Munoz, Nicolas Vandapel, Martial Hebert	Onboard contextual classification of 3-D point clouds with learned high-order Markov Random Fields.	ICRA	2009	DBLP DOI BibTeX RDF
1	Mary Jean Harrold	Reduce, reuse, recycle, recover: Techniques for improved regression testing.	ICSM	2009	DBLP DOI BibTeX RDF
1	Truong Vinh Truong Duy, Yukinori Sato, Yasushi Inoguchi	Improving accuracy of host load predictions on computational grids by artificial neural networks.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Kazune Miyagi, Hiroshi Shimoda, Hirotake Ishii, Kenji Enomoto, Mikio Iwakawa, Masaaki Terano	Development of an Evaluation Method for Office Work Productivity.	HCI	2009	DBLP DOI BibTeX RDF	performance test, cognitive ability, office environment, fNIRS
1	Mirza Mahmood Baig, Ansar Ahmad Khan	A Formal Technique for Reducing Software Testing Time Complexity.	SCSS	2008	DBLP DOI BibTeX RDF
1	Kanad Basu, Prabhat Mishra	A novel test-data compression technique using application-aware bitmask and dictionary selection methods.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	compression, test data, decompression
1	Gregory M. Kapfhammer, Mary Lou Soffa	Database-aware test coverage monitoring.	ISEC	2008	DBLP DOI BibTeX RDF	test coverage monitoring, database application
1	Praveen Ranjan Srivastava, Deepak Pareek, Kailash Sati, Dinesh C. Pujari, G. Raghurama	Non homogenous poisson process based cumulative priority model for determining optimal software testing period.	ACM SIGSOFT Software Engineering Notes	2008	DBLP DOI BibTeX RDF	cumulative priority, optimal testing policy, software life cycle length, software release time, non homogenous poisson process
1	Renato Donini, Stefano Marrone, Nicola Mazzocca, Antonio Orazzo, Domenico Papa, Salvatore Venticinque	Testing Complex Safety-Critical Systems in SOA Context.	CISIS	2008	DBLP DOI BibTeX RDF
1	Feng Yuan, Lin Huang, Qiang Xu	Re-Examining the Use of Network-on-Chip as Test Access Mechanism.	DATE	2008	DBLP DOI BibTeX RDF
1	Jia Li, Qiang Xu, Yu Hu, Xiaowei Li	Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.	DELTA	2008	DBLP DOI BibTeX RDF	NoC channel utilization, test wrapper, interleaved test scheduling
1	Lingling Zhang, Jie Wei, Anqiang Huang, Jun Li, Peng Zhang	DEA-Based Comprehensive Evaluation of Intelligent Knowledge.	Web Intelligence/IAT Workshops	2008	DBLP DOI BibTeX RDF
1	Shan-Shan Hou, Lu Zhang 0023, Tao Xie, Jiasu Sun	Quota-constrained test-case prioritization for regression testing of service-centric systems.	ICSM	2008	DBLP DOI BibTeX RDF
1	Tomotaka Ishii, Tadashi Dohi	A New Paradigm for Software Reliability Modeling - From NHPP to NHGP.	PRDC	2008	DBLP DOI BibTeX RDF
1	Yun Liu, Zhijie Gan, Yu Sun	Static Hand Gesture Recognition and its Application based on Support Vector Machines.	SNPD	2008	DBLP DOI BibTeX RDF
1	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee	System-Level Specification Testing Of Wireless Transceivers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Fabrizio Lombardi	Substrate Testing on a Multi-Site/Multi-Probe ATE.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Substrate testing, Multi-probe, ATE, MCM, Manufacturing test, Multi-site
1	K. Bommanna Raja, M. Madheswaran, K. Thyagarajah	A Hybrid Fuzzy-Neural System for Computer-Aided Diagnosis of Ultrasound Kidney Images Using Prominent Features.	J. Medical Systems	2008	DBLP DOI BibTeX RDF	US kidney image analysis, Multi-layer back propagation network, Fuzzy-neural system, Kidney classification, Feature extraction, Computer-aided diagnosis
1	Hai Lin	Critique of Traditional Statistical Tests in Asset Pricing Models.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
1	Gregorio Díaz, Elena Navarro, María-Emilia Cambronero, Valentin Valero, Fernando Cuartero	Testing Time Goal-Driven Requirements with Model Checking Techniques.	ECBS	2007	DBLP DOI BibTeX RDF
1	Sébastien Baehni, João Barreto, Patrick Eugster, Rachid Guerraoui	Efficient distributed subtyping tests.	DEBS	2007	DBLP DOI BibTeX RDF	Java, event, type, subtype, conformance
1	Raúl A. Santelices, Mary Jean Harrold	Efficiently monitoring data-flow test coverage.	ASE	2007	DBLP DOI BibTeX RDF	definition-use association, inference, instrumentation, test coverage, data-flow testing
1	Adam M. Smith, Joshua Geiger, Gregory M. Kapfhammer, Mary Lou Soffa	Test suite reduction and prioritization with call trees.	ASE	2007	DBLP DOI BibTeX RDF	call trees, regression testing
1	Domenico Cotroneo, Roberto Pietrantuono, Leonardo Mariani, Fabrizio Pastore	Investigation of failure causes in workload-driven reliability testing.	SOQUA	2007	DBLP DOI BibTeX RDF	JVM monitoring, model inference, workloads execution, log file analysis, automated analysis
1	Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty	SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.	DAC	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay	A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Anshuman Chandra, Haihua Yan, Rohit Kapur	Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.	VTS	2007	DBLP DOI BibTeX RDF
1	Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen	A Built-In Self-Repair Scheme for Multiport RAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A New ATPG Technique (ExpoTan) for Testing Analog Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty	Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Anuja Sehgal, Krishnendu Chakrabarty	Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
1	Shinji Inoue, Shigeru Yamada	Generalized Discrete Software Reliability Modeling With Effect of Program Size.	IEEE Transactions on Systems, Man, and Cybernetics, Part A	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay	Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach.	ICIC	2007	DBLP DOI BibTeX RDF	wrapper design, test scheduling, test access mechanism, SOC testing
1	Shirong Zhang, Kuanjiu Zhou, Yuan Tian	An Improved NN-SVM Based on K Congener Nearest Neighbors Classification Algorithm.	KSEM	2007	DBLP DOI BibTeX RDF
1	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
1	Kristen R. Walcott, Mary Lou Soffa, Gregory M. Kapfhammer, Robert S. Roos	TimeAware test suite prioritization.	ISSTA	2006	DBLP DOI BibTeX RDF	genetic algorithms, test prioritization, coverage testing
1	Fei Su, Sule Ozev, Krishnendu Chakrabarty	Concurrent testing of digital microfluidics-based biochips.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	microfluidics, biochips, Concurrent testing, catastrophic faults
1	Collin Mulliner, Giovanni Vigna	Vulnerability Analysis of MMS User Agents.	ACSAC	2006	DBLP DOI BibTeX RDF	Multimedia Messaging Service, Mobile devices, Mobile phones, Vulnerability Analysis, Fuzzing
1	Jiann-Chyi Rau, Chien-Shiun Chen, Po-Han Wu	Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Qiang Xu, Baosheng Wang, F. Y. Young	Retention-Aware Test Scheduling for BISTed Embedded SRAMs.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Hassiba Nemmour, Youcef Chibani	Multi-Class SVMs Based on Fuzzy Integral Mixture for Handwritten Digit Recognition.	GMAI	2006	DBLP DOI BibTeX RDF
1	Bum Lim, Jin Kim, Kwang Shim	Hierarchical Load Testing Architecture using Large Scale Virtual Clients.	ICME	2006	DBLP DOI BibTeX RDF
1	Jing Yang, Xue Yang, Jianpei Zhang	A Parallel Multi-Class Classification Support Vector Machine Based on Sequential Minimal Optimization.	IMSCCS	2006	DBLP DOI BibTeX RDF	Support Vector Machine, Parallel, Decision Tree, Multi-Class Classification, Sequential Minimal Optimization
1	Amit Laknaur, Haibo Wang	Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits.	ISQED	2006	DBLP DOI BibTeX RDF
1	Tomotaka Ishii, Tadashi Dohi	Two-Dimensional Software Reliability Models and Their Application.	PRDC	2006	DBLP DOI BibTeX RDF	Test-execution time, Two-dimensional models, Bivariate fault-detection time distributions, Software reliability, Non-homogeneous Poisson processes, Testing effort
1	Qiang Xu, Nicola Nicolici	DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	embedded core delay test, System-on-a-chip
1	Fang Liu, Yun Tian	Intrusion Detection Based on Clustering Organizational Co-Evolutionary Classification.	FSKD	2006	DBLP DOI BibTeX RDF
1	P. A. Vijaya, M. Narasimha Murty, D. K. Subramanian	Efficient median based clustering and classification techniques for protein sequences.	Pattern Anal. Appl.	2006	DBLP DOI BibTeX RDF	Median strings/sequences, Set median, Clustering, Feature selection, Prototypes, Classification accuracy, Protein sequences
1	Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty	Multi-frequency wrapper design and optimization for embedded cores under average power constraints.	DAC	2005	DBLP DOI BibTeX RDF	scan control unit, wrapper design, multiple clock domains
1	Christoph Csallner, Yannis Smaragdakis	Check 'n' crash: combining static checking and testing.	ICSE	2005	DBLP DOI BibTeX RDF	usability, static analysis, dynamic analysis, automatic testing, test case generation, extended static checking
1	Gregory M. Kapfhammer, Mary Lou Soffa, Daniel Mossé	Testing in resource constrained execution environments.	ASE	2005	DBLP DOI BibTeX RDF	code unloading, test suite execution
1	Achintya Halder, Abhijit Chatterjee	Low-cost Production Test of BER for Wireless Receivers.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Yongsheng Wang, Jinxiang Wang, Fengchang Lai, Yizheng Ye	Optimal Schemes for ADC BIST Based on Histogram.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Maurizio Pighin, Anna Marzona	Reducing Corrective Maintenance Effort Considering Module's History.	CSMR	2005	DBLP DOI BibTeX RDF	Economical aspects of software evolution, Tools and enabling technologies for evolution, Software metrics
1	Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty	Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.	DFT	2005	DBLP DOI BibTeX RDF
1	Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala	A New Test Methodology For DNL Error In Flash ADC's.	DFT	2005	DBLP DOI BibTeX RDF
1	Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos	A processor for testing mixed-signal cores in System-on-Chip.	DSD	2005	DBLP DOI BibTeX RDF
1	Gwo-Jen Hwang, Peng-Yeng Yin, Gwo-Haur Hwang, Ying Chan	A Novel Approach for Composing Test Sheets from Large Item Banks to Meet Multiple Assessment Criteria.	ICALT	2005	DBLP DOI BibTeX RDF
1	Maurizio Pighin, Anna Marzona	Optimizing Test to Reduce Maintenance.	ICSM	2005	DBLP DOI BibTeX RDF
1	Jing Zhao, Hongwei Liu, Gang Cui, Xiao-Zong Yang	Software Reliability Growth Model from Testing to Operation.	ICSM	2005	DBLP DOI BibTeX RDF
1	Pradeep M. Patil, S. N. Kulkarni, A. J. Patil, D. D. Doye, U. V. Kulkarni	Modular General Fuzzy Hypersphere Neural Network.	ICTAI	2005	DBLP DOI BibTeX RDF
1	Ju Yeob Kim, Sung Je Hong, Jong Kim	Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Khaja Mohammad Shazzad, Jong Sou Park	Optimization of Intrusion Detection through Fast Hybrid Feature Selection.	PDCAT	2005	DBLP DOI BibTeX RDF
1	Shiyi Xu	High-Order Syndrome Testing for VLSI Circuits.	PRDC	2005	DBLP DOI BibTeX RDF	Syndrome Testing Minterms, Syndrome, Exhaustive Testing
1	Daniel M. Berry, Daniela Damian, Anthony Finkelstein, Donald C. Gause, Robert Hall, Alan Wassyng	To do or not to do: If the requirements engineering payoff is so good, why aren't more companies doing it?	RE	2005	DBLP DOI BibTeX RDF
1	Stefan Andrei, Wei-Ngan Chin, Albert Mo Kim Cheng, Yongxin Zhu	Runtime-Coordinated Scalable Incremental Checksum Testing of Combinational Circuits.	RTCSA	2005	DBLP DOI BibTeX RDF
1	Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar	Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Dan Zhao, Shambhu J. Upadhyaya	Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Qiang Xu, Nicola Nicolici	Wrapper design for multifrequency IP cores.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF