Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	John V. A. Janeri, Daylan B. Darby, Daniel D. Schnackenberg	Building higher resolution synthetic clocks for signaling in covert timing channels.	CSFW	1995	DBLP DOI BibTeX RDF	higher resolution synthetic clocks, timing channel countermeasure, Boeing multilevel secure local area network, secure network server, internal timing channels, time reference clock granularity, fine-grained signaling clock, timing channel throughput, timing channel capacities, local area networks, security of data, worst-case analysis, covert timing channels
6	Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
6	Aloysius K. Mok, Guangtian Liu	Early detection of timing constraint violation at runtime.	RTSS	1997	DBLP DOI BibTeX RDF	timing constraint violation detection, timing constraint compliance, conditional guarantees, satisfiability checking algorithm, timing constraint monitoring, time terms, timing constraint specification, real-time systems, real time applications
6	Leo Motus, R. Kinksaar, Tonu Naks, M. Pall	Enhancing object modelling technique with timing analysis capabilities.	ICECCS	1995	DBLP DOI BibTeX RDF	enhanced object modelling technique, timing analysis capabilities, timing correctness, software implementation problems, specification problems, time-constraint elicitation, Q-model, noncontradiction analysis, time modelling requirements, performance, software engineering, real-time systems, real-time systems, data integrity, timing, scheduling algorithms, timing constraints, object-oriented methods, consistency checking, application domain, integrity checking, design problems
5	Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin	How accurately can we model timing in a placement engine?	DAC	2005	DBLP DOI BibTeX RDF	differential timing analysis, linear programming, static timing analysis, timing-driven placement
5	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
5	Markus Lindgren, Hans Hansson, Henrik Thane	Using measurements to derive the worst-case execution time.	RTCSA	2000	DBLP DOI BibTeX RDF	execution time analysis, program flow analysis, low level timing information, low level timing analysis, program execution times, timing measurements, instrumented version, program fragments, non-exhaustive measurements, program paths, realistic processor model, scheduling, real-time systems, real time systems, embedded systems, worst-case execution time, pipeline processing, schedulability analysis, program diagnostics, architectural modeling, pipeline architectures, flow graphs, timing estimates, target architecture, system of linear equations
5	Uwe Fassnacht, Jürgen Schietke	Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset.	DATE	1998	DBLP DOI BibTeX RDF	Timing, static timing analysis, timing optimization
5	Tai M. Chung, Henry G. Dietz	Static scheduling of hard real-time code with instruction-level timing accuracy.	RTCSA	1996	DBLP DOI BibTeX RDF	timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
5	Lo Ko, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon	Supporting the specification and analysis of timing constraints. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	timing constraints analysis, real-time programmers, user-friendly environment, user specification, real-time systems, user interface, formal specification, timing, synchronisation, timing constraints, computer aided software engineering, C language, C program, project support environments
5	R. K. Gupta	A framework for interactive analysis of timing constraints in embedded systems.	CODES	1996	DBLP DOI BibTeX RDF	constraint satisfiability, performance evaluation, real-time systems, embedded systems, timing, computability, logic design, satisfiability, timing constraints, interactive analysis, timing performance
5	Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen	A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers.	VTS	1995	DBLP DOI BibTeX RDF	emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing
5	Vinod Narayananan, David LaPotin, Rajesh K. Gupta, Gopalakrishnan Vijayan	PEPPER - a timing driven early floorplanner. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
5	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
5	Anirudh Devgan	Accurate device modeling techniques for efficient timing simulation of integrated circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	device modeling techniques, Fast-to-evaluate and Accurate Simplified Transistor, aggressive MOS technologies, FAST models, timing, AGES, circuit analysis computing, integrated circuits, circuit simulators, transient analysis, transistors, transistor, transient simulator, timing simulation, timing simulator, electronic engineering computing, semiconductor device models
4	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
4	Dipankar Das 0002, P. P. Chakrabarti, Rajeev Kumar	Scenario-based timing verification of multiprocessor embedded applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	execution scenarios, real time systems, static timing analysis, Timing verification
4	James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi	A stochastic jitter model for analyzing digital timing-recovery circuits.	DAC	2009	DBLP DOI BibTeX RDF	delay-locked loop (DLL), mean-time-between-failures (MTBF), timing margins, timing recovery circuits, Markov chain, stochastic model, jitter, bit-error-rate (BER)
4	Seyed-Abdollah Aftabjahani, Linda S. Milor	Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis
4	David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
4	Sibin Mohan, Frank Mueller	Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	hybrid timing anlalysis, hardware/software interactions, real-time systems, embedded systems, computer architecture, timing analysis, worst-case execution time, out-of-order execution
4	Ho Kyoung Lee, Woo Jin Lee, Heung Seok Chae, Yong Rae Kwon	Specification and analysis of timing requirements for real-time systems in the CBD approach.	Real-Time Systems	2007	DBLP DOI BibTeX RDF	Real-time system, Petri nets, Component, Timing analysis, Timing constraints, CBD, Compositional analysis
4	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
4	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
4	Renaud Jolivet, Alexander Rauch, Hans-Rudolf Lüscher, Wulfram Gerstner	Predicting spike timing of neocortical pyramidal neurons by simple threshold models.	Journal of Computational Neuroscience	2006	DBLP DOI BibTeX RDF	Spike Response Model, Stochastic input, Spike-timing reliability, Predicting spike timing, Adapting threshold
4	Ali Dasdan, Ivan Hom	Handling inverted temperature dependence in static timing analysis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	timing corners, voltage dependence, Static timing analysis, temperature dependence
4	Farid N. Najm, Noel Menezes	Statistical timing analysis based on a timing yield model.	DAC	2004	DBLP DOI BibTeX RDF	statistical timing analysis, principal components, timing yield
4	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
4	Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
4	Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer	TA-PSV - Timing Analysis for Partially Specified Vectors.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	timing analysis for partially specified vectors (TA-PSV), crosstalk test generation (ATPG), static timing analysis (STA), delay model
4	Peter A. Beerel, Ken S. Stevens, Hoshik Kim	Relative Timing Based Verification of Timed Circuits and Systems.	ASYNC	2002	DBLP DOI BibTeX RDF	Relative Timing, Verification and Timed Circuits, Timing Constraints
4	Martin Foltin, Brian Foutz, Sean Tyler	Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.	DAC	2002	DBLP DOI BibTeX RDF	timing analysis, VLSI design, timing model, circuit optimization
4	Jing Zeng, Magdy S. Abadir, Jacob A. Abraham	False timing path identification using ATPG techniques and delay-based information.	DAC	2002	DBLP DOI BibTeX RDF	false timing paths, timing slack, ATPG, static timing analysis
4	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
4	Avi Efrati, Moshe Kleyner	Timing analysis challenges for high speed CPUs at 90nm and below.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
4	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula	Statistical timing analysis using bounds and selective enumeration.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
4	Ali Dasdan	Efficient algorithms for debugging timing constraint violations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
4	Xuandong Li, Johan Lilius	Checking compositions of UML sequence diagrams for timing inconsistency.	APSEC	2000	DBLP DOI BibTeX RDF	UML sequence diagram composition checking, timing inconsistency checking, real-time systems specification, system behaviour scenarios, high-level graphs, real-time systems, model checking, Unified Modeling Language, formal verification, graphs, timing, specification languages, sequences, diagrams, object interactions
4	Stanislav Polonsky, Moyra K. McManus, Daniel R. Knebel, Steve Steen, Pia Sanda	Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	imaging circuit analysis, IBM G6 microprocessor, non-invasive backside timing, Picosecond Imaging Circuit Analysis, waveform extraction, integrated circuit testing, timing analysis, race condition, circuit switching, integrated memory circuits, hazards and race conditions, L1 cache
4	Stephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
4	Håkan Sundell, Philippas Tsigas	Space efficient wait-free buffer sharing in multiprocessor real-time systems based on timing information.	RTCSA	2000	DBLP DOI BibTeX RDF	space-efficient wait-free algorithm, real-time multiprocessor systems, deadline guarantees, nonblocking algorithms, unbounded time-stamps, time-stamp bounding, concurrent read/write operations, real-time systems, protocol, data structures, data structures, timing, multiprocessing systems, mutual exclusion, blocking, buffer storage, timing information, shared buffer, memory protocols
4	Yu-Sheng Huang, Chih-wen Hsueh	Minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model.	RTCSA	2000	DBLP DOI BibTeX RDF	maximum end-to-end delay minimisation, distributed pinwheel model, end-to-end timing requirements, tight maximum delay bound, quality of service, Internet, computational complexity, timing, computer networks, heuristic algorithm, processor scheduling, timing constraints, simulation result, distributed real-time systems, tree structure, heuristic programming, NP-hard problems, linear-time algorithm, pipeline structure
4	Thomas Lundqvist, Per Stenström	Timing Anomalies in Dynamically Scheduled Microprocessors.	RTSS	1999	DBLP DOI BibTeX RDF	timing anomaly, Real-time systems, resource allocation, timing analysis, worst-case execution time, out-of-order execution, dynamically scheduled processor
4	Eduard Cerny, Fen Jin	Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming.	ICCD	1999	DBLP DOI BibTeX RDF	Interface verification, interface controllers, relational interval arithmetic, constraint logic programming, timing verification, timing diagrams
4	Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta	A timing-driven design and validation methodology for embedded real-time systems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification
4	Karim Khordoc, Eduard Cerny	Semantics and verification of action diagrams with linear timing.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	compatibility of interfaces, hardware interfaces, causality, timing verification, timing diagrams
4	Rung-Bin Lin, Meng-Chiou Wu	A New Statistical Approach to Timing Analysis of VLSI Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Statistical timing anylysis, longest path delay, path correlation, timing simulation
4	Wendy Belluomini, Chris J. Myers	Efficient Timing Analysis Algorithms for Timed State Space Exploration.	ASYNC	1997	DBLP DOI BibTeX RDF	timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders
4	Mukund Sivaraman, Andrzej J. Strojwas	Timing analysis based on primitive path delay fault identification.	ICCAD	1997	DBLP DOI BibTeX RDF	primitive path delay faults, correlated delay, floating mode, timing analysis, timing verification, false path, path delay fault testing
4	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
4	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
4	Hakan Yalcin, John P. Hayes, Karem A. Sakallah	An approximate timing analysis method for datapath circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Approximate timing analysis, conditional delay matrix, delay calculation, hierarchical timing models, signal propagation conditions
4	Peter Walker, Sumit Ghosh	On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics
4	Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij	The MSP.RTL real-time scheduler synthesis tool.	RTSS	1996	DBLP DOI BibTeX RDF	MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic
4	Jeffrey J. P. Tsai, Steve Jennhwa Yang, Yao-Hsiung Chang	Timing Constraint Petri Nets and Their Application to Schedulability Analysis of Real-Time System Specifications.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	real-time systems, Petri nets, synthesis, timing analysis, Timing constraints, time Petri nets, timed Petri nets, specification and verification
4	Shuichi Oikawa, Hideyuki Tokuda	Efficient timing management for user-level real-time threads. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	efficient timing management, user-level real-time threads, specified time, upcalled user-level scheduler, user-level scheduler overhead, shared user-level timers, shared kernel/user structure, upcall performance, scheduling, performance evaluations, software engineering, real-time systems, resource allocation, timing, shared memory systems, kernel, processor scheduling, software performance evaluation, operating system kernels, hints, virtual processor
4	Hakan Yalcin, John P. Hayes	Hierarchical timing analysis using conditional delays.	ICCAD	1995	DBLP DOI BibTeX RDF	Hierarchical timing analysis, conditional delays, symbolic analysis, timing modeling, path sensitization, high-level modeling
4	Anmol Mathur, K. C. Chen, C. L. Liu	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
4	Ajay J. Daga, William P. Birmingham	A symbolic-simulation approach to the timing verification of interacting FSMs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	symbolic-simulation approach, interacting FSMs, timing verifier, complex sequential circuit verification, combinational paths, inherently modular nature, symbolic simulation verification methodology, formal verification, logic testing, finite state machines, finite state machines, sequential circuits, circuit analysis computing, timing verification
4	Gary S. H. Tan, Yong Meng Teo	Experiences in simulating a declarative multiprocessor.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	declarative multiprocessor simulation, declarative programming languages, Flagship parallel reduction machine, packet-based graph reduction model, executional units, timing characteristics, event-driven timing scheme, tightly-coupled processor-store pairs, performance evaluation, performance evaluation, parallel architectures, virtual machines, timing, parallel machines, synchronisation, synchronisation, parallel languages, functional languages, functional languages, functional simulator, parallel computer architectures, MIMD architecture, delta network
4	Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten	Performance driven standard-cell placement using the genetic algorithm.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	connection length, timing-driven placer, /spl alpha/-criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standard-cell placement
4	Douglas Niehaus, John A. Stankovic, Krithi Ramamritham	A real-time system description language. (PDF / PS)	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	real-time system description language, system design specification, automatic calculation, automatic analysis environment, design and analysis environment, specification changes, layered abstractions, concealed implementation details, timing correctness, robotic pick-and-place circuit board assembly, distributed real-time scheduling simulation, ease of modification, automatic loading, real-time systems, timing, specification languages, timing analysis, SDL, automatic linking, flexible manufacturing
4	Tapan J. Chakraborty, Vishwani D. Agrawal	Simulation of at-speed tests for stuck-at faults.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at fault detectability, at-speed test simulation, delayed signal transitions, timing hazards, fault simulation method, delay-hazard robust test coverage, timing considerations, high performance circuits, fault diagnosis, logic testing, delays, timing, integrated circuit testing, circuit analysis computing, hazards and race conditions, path delays, high speed test
4	Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang	Foresighted Instruction Scheduling Under Timing Constraints.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	foresighted instruction scheduling, minimum timing information, foresighted compaction, data dependency graph arcs, data dependency information, maximum timing information, greedy compaction algorithms, scheduling, parallel algorithms, parallel programming, graph theory, timing constraints, programming theory, list scheduling, look ahead
4	David Hung-Chang Du, S. H. Yen, Subbarao Ghanta	On the General False Path Problem in Timing Analysis.	DAC	1989	DBLP DOI BibTeX RDF	Graph Theory, Timing Analysis, Logic Simulation, VLSI circuit, Timing Verification, False path
4	Aaron J. Gordon, Raphael A. Finkel	Handling Timing Errors in Distributed Programs.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	postmortem debugger, history-keeping mechanism, distributed processing, software tools, program testing, directed graph, directed graphs, distributed programs, interprocess communication, TAP, timing errors, timing graph
3	Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li 0001	Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.	ISCA	2010	DBLP DOI BibTeX RDF	complimentary effects, delay sensor, pvt variations, timing emergency, thread migration
3	John Sartori, Rakesh Kumar	Overscaling-friendly timing speculation architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	stochastic processors, timing speculation, adaptability
3	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
3	Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty	Timing analysis of esterel programs on general-purpose multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	multiprocessor, timing analysis, synchronous language, esterel
3	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
3	Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li	Static timing analysis for flexible TFT circuits.	DAC	2010	DBLP DOI BibTeX RDF	flexible electronics, static timing analysis
3	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
3	Luís Guerra e Silva, Joel R. Phillips, L. Miguel Silveira	Speedpath analysis under parametric timing models.	DAC	2010	DBLP DOI BibTeX RDF	parametric timing models, speedpath analysis
3	Gregory Lucas, Chen Dong, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
3	Johan Nordlander, Rolf Johansson, Risat Mahmud Pathan	Unambiguous semantics in automotive timing modeling.	EDCC-CARS	2010	DBLP DOI BibTeX RDF	modeling, synchronization, delay constraints, timing semantics
3	Hatice Kose-Bagci, Frank Broz, Qiming Shen, Kerstin Dautenhahn, Chrystopher L. Nehaniv	As Time Goes By: Representing and Reasoning About Timing in Human-Robot Interaction Studies.	AAAI Spring Symposium: It's All in the Timing	2010	DBLP BibTeX RDF
3	Wilsaan M. Joiner, Mark Shelhamer	A model of time estimation and error feedback in predictive timing behavior.	Journal of Computational Neuroscience	2009	DBLP DOI BibTeX RDF	Error feedback, Prediction, Timing, Saccade
3	Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang	Lens aberration aware placement for timing yield.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Layout, design for manufacturing, lithography, timing yield
3	Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury, Lothar Thiele	Cache-aware timing analysis of streaming applications.	Real-Time Systems	2009	DBLP DOI BibTeX RDF	Timing analysis, Instruction cache, Streaming applications
3	V. Torres, A. Perez-Pascual, T. Sansaloni, Javier Valls	Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Timing recovery, FPGA, Synchronization, SDR, Feedback loop
3	Scott A. Crosby, Dan S. Wallach, Rudolf H. Riedi	Opportunities and Limits of Remote Timing Attacks.	ACM Trans. Inf. Syst. Secur.	2009	DBLP DOI BibTeX RDF	jitter, timing attacks, Information leakage
3	Wei Dong, Jiandong Li, Zhuo Lu	Joint timing error, frequency offset and channel estimation for MIMO systems.	IWCMC	2009	DBLP DOI BibTeX RDF	frequency offset, MIMO, channel estimation, timing error
3	Joshua Wall, Jamil Y. Khan	Dynamic protocol timing adaptation for improved efficiency in IEEE 802.11 wireless LANs.	IWCMC	2009	DBLP DOI BibTeX RDF	MAC efficiency, dynamic protocol timing, 802.11, CSMA/CA
3	Nuno Laranjeiro, Marco Vieira, Henrique Madeira	Predicting Timing Failures in Web Services.	DASFAA Workshops	2009	DBLP DOI BibTeX RDF	timing failures, web services, prediction, detection
3	Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li 0001	MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.	ISLPED	2009	DBLP DOI BibTeX RDF	efficiency, DVFS, timing adaptability
3	Sherief Reda, Aung Si, R. Iris Bahar	Reducing the leakage and timing variability of 2D ICcs using 3D ICs.	ISLPED	2009	DBLP DOI BibTeX RDF	3D integrated circuit, timing, variability, leakage
3	Wei-Tek Tsai, Hessam S. Sarjoughian, Wu Li, Xin Sun	Timing specification and analysis for service-oriented simulation.	SpringSim	2009	DBLP DOI BibTeX RDF	service-oriented simulation, timing specifications and analysis, DEVS
3	Peng Sun, Rong Luo	Closed-form solution for timing analysis of process variations on SWCNT interconnect.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect, process variation, timing analysis, carbon nanotube, closed-form
3	Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama	A Gaussian mixture model for statistical timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	slew distribution, variability, Gaussian mixture model, statistical timing analysis, delay distribution
3	Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty	Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	design space exploration, timing analysis, automotive
3	Shihheng Tsai, Chung-Yang Huang	A false-path aware formal static timing analyzer considering simultaneous input transitions.	DAC	2009	DBLP DOI BibTeX RDF	critical path selection, multiple input transitioning, formal method, static timing analysis, false path
3	Mihir R. Choudhury, Kartik Mohanram	Timing-driven optimization using lookahead logic circuits.	DAC	2009	DBLP DOI BibTeX RDF	logic synthesis, timing optimization, lookahead
3	Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik	A parametric approach for handling local variation effects in timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	on chip variation (OCV), timing, parametric analysis
3	David D. Ling, Chandu Visweswariah, Peter Feldmann, Soroush Abbaspour	A moment-based effective characterization waveform for static timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	timing analysis, current source model
3	Zhonglei Wang, Andreas Herkersdorf	An efficient approach for system-level timing simulation of compiler-optimized embedded software.	DAC	2009	DBLP DOI BibTeX RDF	iSciSim, software timing simulation, system level design
3	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
3	Emilia Käsper, Peter Schwabe	Faster and Timing-Attack Resistant AES-GCM.	CHES	2009	DBLP DOI BibTeX RDF	Galois/Counter mode, cache-timing attacks, AES, fast implementations
3	Billy Bob Brumley, Risto M. Hakala	Cache-Timing Template Attacks.	ASIACRYPT	2009	DBLP DOI BibTeX RDF	cache-timing attacks, elliptic curve cryptography, side channel attacks
3	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement