Search results for "timing closure"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Anders Edman, Christer Svensson	Timing closure through a globally synchronous, timing partitioned design methodology.	DAC	2004	DBLP DOI BibTeX RDF	wire delays, clock skew, timing closure
3	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
3	Kaijian Shi, Graig Godwin	Hybrid hierarchical timing closure methodology for a high performance and low power DSP.	DAC	2003	DBLP DOI BibTeX RDF	chip integration, methodology, DSP, timing closure, placement optimization
3	Stephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia	"Timing closure by design, " a high frequency microprocessor design methodology.	DAC	2000	DBLP DOI BibTeX RDF	chip integration, dynamic circuits0, CAD, methodology, microprocessor, timing analysis, PLA, timing closure
2	Shashank Prasad, Dongzi Liu, Oleg Levitsky, Dave Noice, Shailendra Srivastava	Post Assembly Timing Closure for Multi Million Gate Chips.	VLSI Design	2010	DBLP DOI BibTeX RDF	optimization, Timing closure
2	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
2	Nobuyuki Nishiguchi	An advance RTL to GDS2 design methodology for 90 nm and below system LSIs to solve timing closure, signal integrity and design for manufacturing.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Nick Kanopoulos	Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.	PATMOS	2004	DBLP DOI BibTeX RDF
2	David S. Kung	Timing closure for low-FO4 microprocessor design.	DAC	2004	DBLP DOI BibTeX RDF	FO4, synthesis, placement, high performance
2	Olivier Omedes, Michel Robert, Mohammed Ramdani	A flexibility aware budgeting for hierarchical flow timing closure.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
2	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
2	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
2	F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
2	Jinan Lou, Wei Chen, Massoud Pedram	Concurrent logic restructuring and placement for timing closure.	ICCAD	1999	DBLP BibTeX RDF
1	Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu	VLSI Physical Design - From Graph Partitioning to Timing Closure.		2011	DOI RDF
1	Michael D. Moffitt, Chin-Ngai Sze	Wire synthesizable global routing for timing closure.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Seokhyun Lee, Kiyoung Choi	High-level synthesis with distributed controller for fast timing closure.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang	Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini	Networks on Chips: from research to products.	DAC	2010	DBLP DOI BibTeX RDF	SoC, system on chip, network on chip, NoC
1	Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Ying Zhou	Ultra-fast interconnect driven cell cloning for minimizing critical path delay.	ISPD	2010	DBLP DOI BibTeX RDF	gate duplication, physical synthesis, timing-driven placement
1	Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu	ITOP: integrating timing optimization within placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, timing optimization, physical synthesis
1	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Fast buffering for optimizing worst slack and resource consumption in repeater trees.	ISPD	2009	DBLP DOI BibTeX RDF	interconnect buffering, repeater tree, physical design, repeater insertion, timing closure
1	Kanupriya Gulati, Sunil P. Khatri	Accelerating statistical static timing analysis using graphics processing units.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang	New spare cell design for IR drop minimization in Engineering Change Order.	DAC	2009	DBLP DOI BibTeX RDF	spare cell, IR drop, decoupling capacitor, ECO
1	Shihheng Tsai, Chung-Yang Huang	A false-path aware formal static timing analyzer considering simultaneous input transitions.	DAC	2009	DBLP DOI BibTeX RDF	critical path selection, multiple input transitioning, formal method, static timing analysis, false path
1	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
1	Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng	Wire shaping is practical.	ISPD	2009	DBLP DOI BibTeX RDF	manufacturing for design, wire tapering, interconnect, opc, power minimization
1	Uday Doddannagari, Shiyan Hu, Weiping Shi	Fast characterization of parameterized cell library.	ISQED	2009	DBLP DOI BibTeX RDF
1	Brent E. Nelson	FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda.	ARC	2009	DBLP DOI BibTeX RDF
1	Keith So	Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.	FPGA	2008	DBLP DOI BibTeX RDF	lexicographic search, negotiated congestion, timing-driven routing, FPGA
1	Huan Ren, Shantanu Dutt	Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan	An integrated nonlinear placement framework with congestion and porosity aware buffer planning.	DAC	2008	DBLP DOI BibTeX RDF	VLSI, placement, physical design, buffer
1	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
1	Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown	Delay driven AIG restructuring using slack budget management.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	aig, budget management, logic synthesis, network flow
1	Shiyan Hu, Zhuo Li, Charles J. Alpert	A polynomial time approximation scheme for timing constrained minimum cost layer assignment.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia	Fast interconnect synthesis with layer assignment.	ISPD	2008	DBLP DOI BibTeX RDF	buffer insertion, wire sizing, layer assignment, interconnect synthesis
1	Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov	The coming of age of (academic) global routing.	ISPD	2008	DBLP DOI BibTeX RDF	optimization, routing, VLSI, benchmarks, computer-aided design, congestion, global routing, wirelength
1	David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.	ISPD	2008	DBLP DOI BibTeX RDF	static timing analysis, timing-driven placement
1	Phiroze N. Parakh, Shankar Krishnamoorthy	A robust approach to lithography friendly design implementation.	ISPD	2008	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Erik Jan Marinissen	Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.	DATE	2008	DBLP DOI BibTeX RDF
1	Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal	How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.	DSD	2008	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	Custom rotary clock router.	ICCD	2008	DBLP DOI BibTeX RDF
1	Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.	NOCS	2008	DBLP DOI BibTeX RDF
1	David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov	RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	S. Srivastava, J. Roychowdhury	Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki	A Novel Routing Architecture for Field-Programmable Gate-Arrays.	ARCS	2008	DBLP DOI BibTeX RDF
1	Deshanand P. Singh, Stephen Dean Brown	An area-efficient timing closure technique for FPGAs using Shannon's expansion.	Integration	2007	DBLP DOI BibTeX RDF
1	Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis	Efficient timing closure with a transistor level design flow.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Ali Jahanian, Morteza Saheb Zamani	Improved timing closure by early buffer planning in floor-placement design flow.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, design convergence, buffer insertion
1	Ozgur Sinanoglu, Philip Schremmer	Diagnosis, modeling and tolerance of scan chain hold-time violations.	DATE	2007	DBLP DOI BibTeX RDF
1	Shweta Srivastava, Jaijeet S. Roychowdhury	Rapid and accurate latch characterization via direct Newton solution of setup/hold times.	DATE	2007	DBLP DOI BibTeX RDF
1	Jongyoon Jung, Taewhan Kim	Timing variation-aware high-level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis	Maze routing steiner trees with effective critical sink optimization.	ISPD	2007	DBLP DOI BibTeX RDF	timing driven synthesis, Steiner trees, maze routing
1	Shankar Krishnamoorthy	Variation and litho driven physical implementation system.	ISPD	2007	DBLP DOI BibTeX RDF	multi-variation optimization, VLSI, lithography
1	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
1	Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz	The nuts and bolts of physical synthesis.	SLIP	2007	DBLP DOI BibTeX RDF
1	Cheoljoo Jeong, Steven M. Nowick	Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Min Pan, Chris C. N. Chu	IPR: An Integrated Placement and Routing Algorithm.	DAC	2007	DBLP DOI BibTeX RDF
1	Shweta Srivastava, Jaijeet S. Roychowdhury	Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.	DAC	2007	DBLP DOI BibTeX RDF
1	Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry	A Low-Power Multi-Pin Maze Routing Methodology.	ISQED	2007	DBLP DOI BibTeX RDF
1	Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalkar, Luca P. Carloni	Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Karim Arabi, Resve A. Saleh, Xiongfei Meng	Power Supply Noise in SoCs: Metrics, Management, and Measurement.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	metrics, DFT, power supply noise, deep-submicron, production test, power integrity
1	Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang	A GALS Infrastructure for a Massively Parallel Multiprocessor.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
1	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Kenta Yamada, Noriaki Oda	Statistical corner conditions of interconnect delay (corner LPE specifications).	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Francisco-Javier Veredas, Hans-Jörg Pfleiderer	Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.	FPL	2006	DBLP DOI BibTeX RDF
1	Vijay Sundaresan, Ranga Vemuri	A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer	Regular Routing Architecture for a LUT-based MPGA.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Siva Embanath, Ramakrishnan Venkata	Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG).	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Rajendra M. Patrikar, Olivier Peyran	Design Planning for Uniform Thermal Distribution.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Chuan Lin, Jia Wang, Hai Zhou	Clustering for Processing Rate Optimization.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Junhyung Um, Taewhan Kim	Resource Sharing Combined with Layout Effects in High-Level Synthesis.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	resource allocation, high-level synthesis, layout
1	Love Singhal, Elaheh Bozorgzadeh	Fast timing closure by interconnect criticality driven delay relaxation.	ICCAD	2005	DBLP BibTeX RDF
1	Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz	Placement stability metrics.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Azadeh Davoodi, Ankur Srivastava	Simultaneous floorplanning and resource binding: a probabilistic approach.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif	An efficient surface-based low-power buffer insertion algorithm.	ISPD	2005	DBLP DOI BibTeX RDF	low-power design, buffer insertion, physical synthesis
1	Paul Villarrubia	Physical design tools for hierarchy.	ISPD	2005	DBLP DOI BibTeX RDF
1	Yuantao Peng, Xun Liu	RITC: Repeater Insertion with Timing Target Compensation.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar	A Framework for Distributed and Hierarchical Design-for-Test.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Haoxing Ren, David Zhigang Pan, David S. Kung	Sensitivity guided net weighting for placement-driven synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Azadeh Davoodi, Ankur Srivastava	Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Yi-Hui Cheng, Yao-Wen Chang	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Tao Jiang, Eric Pettus, Daksh Lehther	A mixed-mode extraction flow for high performance microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Keoncheol Shin, Taewhan Kim	An integrated approach to timing-driven synthesis and placement of arithmetic circuits.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze, Jiang Hu, Charles J. Alpert	A place and route aware buffered Steiner tree construction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Donna Nakano, Erric Solomon	Task oriented visual interface for debugging timing problems in hardware design.	AVI	2004	DBLP DOI BibTeX RDF	cognitive model of users, information visualization, visual interface design
1	Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay	Fast and flexible buffer trees that navigate the physical layout environment.	DAC	2004	DBLP DOI BibTeX RDF	global routing, buffer insertion, physical synthesis
1	Paul K. Rodman	Forest vs. trees: where's the slack?	DAC	2004	DBLP DOI BibTeX RDF
1	Haoxing Ren, David Zhigang Pan, David S. Kung	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
1	Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen	Sensitivity guided net weighting for placement driven synthesis.	ISPD	2004	DBLP DOI BibTeX RDF	interconnect, sensitivity analysis, physical synthesis, timing driven placement, net weight
1	Andrew B. Kahng, Igor L. Markov, Sherief Reda	Boosting: Min-Cut Placement with Improved Signal Delay.	DATE	2004	DBLP DOI BibTeX RDF
1	A. P. Niranjan, Paul C. Wiscombe	Islands of Synchronicity, a Design Methodology for SoC Design.	DATE	2004	DBLP DOI BibTeX RDF
1	Pascal Nsame, Yvon Savaria	A Customizable Embedded SoC Platform Architecture.	IWSOC	2004	DBLP DOI BibTeX RDF
1	Rajat Gupta	Digital Design: The components of a new paradigm.	VLSI Design	2004	DBLP DOI BibTeX RDF	design for testability, logic design, Design methodology, microprocessors, digital integrated circuits
1	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF