Search results for "toggles"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Christopher Ahlberg, Erik Wistrand	IVEE: an Information Visualization and Exploration Environment.	INFOVIS	1995	DBLP DOI BibTeX RDF	Information Visualization and Exploration Environment, IVEE, automatic dynamic query creation, database relations, query devices, multiple visualizations, starfields, multiple query devices, alphasliders, toggles, arbitrary graphical objects, database objects, details-on-demand retrieval, HTML file, multiple IVEE clients, user actions, network, query processing, maps, computer animation, data visualisation, multimedia computing, workstations, query formulation, sliders, multimedia information
1	Mainak Banga, Michael S. Hsiao	A Novel Sustained Vector Technique for the Detection of Hardware Trojans.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Alexander G. Churbanov, Stephen Winters-Hilt	Clustering ionic flow blockade toggles with a Mixture of HMMs.	BMC Bioinformatics	2008	DBLP DOI BibTeX RDF
1	Hui-Chin Yang, Li-Ming Wang, Chung-Ping Chung	iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Xijiang Lin, Yu Huang 0005	Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan shift, Low power test, Scan test, Signal probability
1	Julien Lamoureux, Steven J. E. Wilton	Clock-Aware Placement for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula	Controllability-driven Power Virus Generation for Digital Circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula	Power Virus Generation Using Behavioral Models of Circuits.	VTS	2007	DBLP DOI BibTeX RDF	Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
1	Julien Lamoureux, Steven J. E. Wilton	Architecture and CAD for FPGA Clock Networks.	FPL	2006	DBLP DOI BibTeX RDF
1	Hussam Mousa, Chandra Krintz	HPS: Hybrid Profiling Support.	IEEE PACT	2005	DBLP DOI BibTeX RDF
1	Man Guo, M. Omair Ahmad, M. N. S. Swamy, Chunyan Wang	A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation.	ISCAS	2003	DBLP DOI BibTeX RDF
1	S. C. Leung, Hon Fung Li	A syntax-directed translation for the synthesis of delay-insensitive circuits.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
1	Christian Ronse	Toggles of Openings, and a New Family of Idempotent Operators on Partially Ordered Sets.	Appl. Algebra Eng. Commun. Comput.	1992	DBLP DOI BibTeX RDF