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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 8 keywords
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Results
Found 10 publication records. Showing 10 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 3 | M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li |
Adapting Tomasulo's algorithm for bytecode folding based Java processors.  |
SIGARCH Computer Architecture News  |
2001 |
DBLP DOI BibTeX RDF |
instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming |
| 2 | Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas |
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer.  |
CHARME  |
1999 |
DBLP DOI BibTeX RDF |
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| 2 | Kenneth L. McMillan |
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking.  |
CAV  |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Peter Marwedel, Birgit Sirocic |
Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing.  |
MSE  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Prasad N. Golla, Eric C. Lin |
A Dynamic Scheduling Logic for Exploiting Multiple Functional Units in Single Ship Multithreaded Architectures.  |
SAC  |
1999 |
DBLP DOI BibTeX RDF |
Tomasulo's algorithm, threaded architectures, computer architecture, multithreading, microprocessor |
| 1 | Tamarah Arons, Amir Pnueli |
Verifying Tomasulo's Algoithm by Refinement.  |
VLSI Design  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Kenneth L. McMillan |
Circular Compositional Reasoning about Liveness.  |
CHARME  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Kenneth L. McMillan |
Verification of Infinite State Systems by Compositional Model Checking.  |
CHARME  |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Sergey Berezin, Armin Biere, Edmund M. Clarke, Yunshan Zhu |
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification.  |
FMCAD  |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita |
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.  |
ISCA  |
1989 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #10 of 10 (100 per page; Change: )
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