Search results for "transistor sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
3	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
3	Ian Kuon, Jonathan Rose	Automated transistor sizing for FPGA architecture exploration.	DAC	2008	DBLP DOI BibTeX RDF	optimization, FPGA, transistor sizing
3	Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera	Crosstalk noise optimization by post-layout transistor sizing.	ISPD	2002	DBLP DOI BibTeX RDF	capacitive coupling noise, post-layout optimization, gate sizing, transistor sizing, crosstalk noise
3	Paul I. Pénzes, Mika Nyström, Alain J. Martin	Transistor sizing of energy-delay--efficient circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
3	Abhijit Das	On the Transistor Sizing Problem.	VLSI Design	2000	DBLP DOI BibTeX RDF	Timing Analysis, Timing Optimization, Transistor Sizing, Delay Constraint
3	Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah	Optimization of custom MOS circuits by transistor sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation, optimization, Circuits, gradients, transistor sizing
2	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
2	Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani	Application Specific Transistor Sizing for Low Power Full Adders.	ASAP	2009	DBLP DOI BibTeX RDF
2	Lang Lin, Wayne P. Burleson	Analysis and mitigation of process variation impacts on Power-Attack Tolerance.	DAC	2009	DBLP DOI BibTeX RDF	process variation, differential power analysis, Monte Carlo simulation, transistor sizing
2	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
2	Kumar Yelamarthi, Chien-In Henry Chen	Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
2	Jie Gu, Hanyong Eom, Chris H. Kim	Sleep transistor sizing and control for resonant supply noise damping.	ISLPED	2007	DBLP DOI BibTeX RDF	resonant supply noise, sleep transistor, damping
2	M. Emadi, A. Jafargholi, H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, J. Ghasemi	Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
2	Zhaojun Wo, Israel Koren	Effective analytical delay model for transistor sizing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel	Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel	A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.	SBCCI	2003	DBLP DOI BibTeX RDF
2	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	Fast and exact transistor sizing based on iterative relaxation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Stephanie Augsburger, Borivoje Nikolic	Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction.	ICCD	2002	DBLP DOI BibTeX RDF
2	Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski	Uncertainty-aware circuit optimization.	DAC	2002	DBLP DOI BibTeX RDF	small uncertainty, optimization, process variation, nonlinear, performance optimization, transistor sizing, circuit tuning
2	Paul I. Pénzes, Alain J. Martin	Energy-delay efficiency of VLSI computations.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	energy-delay optimization, transistor sizing
2	Masanori Hashimoto, Hidetoshi Onodera	Post-layout transistor sizing for power reduction in cell-based design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
2	Artur Wróblewski, O. Schumecher, Christian V. Schimpfle, Josef A. Nossek	Minimizing gate capacitances with transistor sizing.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar	A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar	Convex delay models for transistor sizing.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
2	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	MINFLOTRANSIT: min-cost flow based transistor sizing tool.	DAC	2000	DBLP DOI BibTeX RDF
2	Sachin S. Sapatnekar, Weitong Chuang	Power-delay optimizations in gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	optimization, power estimation, VLSI layout, transistor sizing
2	Tong Xiao, Malgorzata Marek-Sadowska	Crosstalk Reduction by Transistor Sizing.	ASP-DAC	1999	DBLP DOI BibTeX RDF
2	James Kao, Anantha Chandrakasan, Dimitri Antoniadis	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.	DAC	1997	DBLP DOI BibTeX RDF
2	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for low power CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Jason Cong, Lei He	An efficient approach to simultaneous transistor and interconnect sizing.	ICCAD	1996	DBLP DOI BibTeX RDF	CH-posynomial programs, STIS, driver/buffer, transistor and interconnect sizing, wire sizing problem, circuit CAD, transistor sizing
2	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
2	Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
2	William H. Kao, Nader Fathi, Chia-Hao Lee	Algorithms for automatic transistor sizing in CMOS digital circuits.	DAC	1985	DBLP DOI BibTeX RDF
1	Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Stephanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander, Marie-Minerve Louërat	A seamless representation for coupling transistor sizing with nanometric CMOS layout generation.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, Vaez Iravani	Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang	Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hiroaki Yoshida, Masahiro Fujita	Performance-Constrained Transistor Sizing for Different Cell Count Minimization.	JIP	2010	DBLP DOI BibTeX RDF
1	Matthias W. Blesken, Sven Lütkemeier, Ulrich Rückert	Multiobjective optimization for transistor sizing sub-threshold CMOS logic standard cells.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Yu Sun, Li-yi Xiao, Cong Shi	DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Jie Gu, Hanyong Eom, John Keane, Chris H. Kim	Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang	Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija	A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).	PATMOS	2009	DBLP DOI BibTeX RDF
1	Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung	Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta	Device/circuit interactions at 22nm technology node.	DAC	2009	DBLP DOI BibTeX RDF	22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs
1	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	JCP	2008	DBLP DOI BibTeX RDF
1	Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo	Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
1	Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram	NBTI-aware flip-flop characterization and design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	device aging, setup and hold times, static timing analysis, NBTI, circuit reliability
1	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
1	Hiroaki Yoshida, Masahiro Fujita	Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.	DATE	2008	DBLP DOI BibTeX RDF
1	Hamed Abrishami, Safar Hatami, Massoud Pedram	Characterization and design of sequential circuit elements to combat soft error.	ICCD	2008	DBLP DOI BibTeX RDF
1	Kian Haghdad, Mohab Anis	Design-Specific Optimization Considering Supply and Threshold Voltage Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa	Transistor Sizing of LCD Driver Circuit for Technology Migration.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang	Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.	DAC	2007	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.	DATE	2007	DBLP DOI BibTeX RDF
1	Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang	A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	DSTN, low power, MTCMOS, sleep transistor
1	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Kiran Puttaswamy, Gabriel H. Loh	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
1	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
1	Liang Wang, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
1	Cristiano Lazzari, Cristiano Santos, Adriel Ziesemer, Lorena Anghel, Ricardo Reis	Efficient timing closure with a transistor level design flow.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Adriel Ziesemer, Cristiano Lazzari	Transistor level automatic layout generator for non-complementary CMOS cells.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Vishal Khandelwal, Ankur Srivastava	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Transistor Sizing of Logic Gates to Maximize Input Delay Variability.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Fatemeh Aezinia, Ali Afzali-Kusha, Caro Lucas	Optimizing High Speed Flip-Flop Using Genetic Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
1	André K. Nieuwland, Samir Jasarevic, Goran Jerin	Combinational Logic Soft Error Analysis and Protection.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Pankaj Golani, Peter A. Beerel	High-Performance Noise-Robust Asynchronous Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Quming Zhou, Kartik Mohanram	Gate sizing to radiation harden combinational logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Massimo Alioto, Gaetano Palumbo	Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta	Optimization of Master-Slave Flip-Flops for High-Performance Applications.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Anand Ramalingam, Bin Zhang 0011, Anirudh Devgan, David Z. Pan	Sleep transistor sizing using timing criticality and temporal currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu	Functionality directed clustering for low power MTCMOS design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Hiran Tennakoon, Carl Sechen	Efficient and accurate gate sizing with piecewise convex delay models.	DAC	2005	DBLP DOI BibTeX RDF	piecewise convex, optimization, Lagrangian relaxation, gate sizing, delay modeling
1	Zhaojun Wo, Israel Koren, Maciej J. Ciesielski	An ILP Formulation for Yield-driven Architectural Synthesis.	DFT	2005	DBLP DOI BibTeX RDF
1	C. Santos, D. Ferrao, R. Reis, J. L. Guntzel	Incremental timing optimization for automatic layout generation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast comparisons of circuit implementations.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Design of Variable Input Delay Gates for Low Dynamic Power Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Mohammad M. Mansour, Naresh R. Shanbhag	A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	turbo-decoding message-passing algorithm, VLSI decoder architectures, LDPC codes, Ramanujan graphs
1	Jo C. Ebergen, Jonathan Gainsley, Paul Cunningham	Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Fang Fang, Jianwen Zhu	Automatic process migration of datapath hard IP libraries.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De	Design optimizations for microprocessors at low temperature.	DAC	2004	DBLP DOI BibTeX RDF	electrothermal modeling, low temperature, refrigeration, power, microprocessor, CMOS, frequency, cooling
1	Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen	Efficient timing closure without timing driven placement and routing.	DAC	2004	DBLP DOI BibTeX RDF	digital design flow, gate sizing, placement and routing, timing closure
1	Vishal Khandelwal, Ankur Srivastava	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Quming Zhou, Kartik Mohanram	Cost-effective radiation hardening technique for combinational logic.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Jo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins	A Fast and Energy-Efficient Stack.	ASYNC	2004	DBLP DOI BibTeX RDF
1	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast Comparisons of Circuit Implementations.	DATE	2004	DBLP DOI BibTeX RDF
1	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
1	Eren Kursun, Soheil Ghiasi, Majid Sarrafzadeh	Transistor Level Budgeting for Power Optimization.	ISQED	2004	DBLP DOI BibTeX RDF
1	Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey	SRAM Leakage Suppression by Minimizing Standby Supply Voltage.	ISQED	2004	DBLP DOI BibTeX RDF
1	Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Performance Metric Based Optimization Protocol.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mandeep Singh, Israel Koren	Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Ricardo Augusto da Luz Reis	Power and Timing Driven Physical Design Automation.	PATMOS	2003	DBLP DOI BibTeX RDF