Search results for "transition fault"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Chung-Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang	MT-SIM a mixed-level transition fault simulator based on parallel patterns.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	mixed-level, parallel pattern, Fault simulation, transition fault
2	Zhen Chen, Boxue Yin, Dong Xiang	Conflict driven scan chain configuration for high transition fault coverage and low test power.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Iwan Tabakow	Using Place and Transition Fault Net Models for Sequential Diagnosis Time Assessment in Discrete Event Systems.	IEA/AIE	2008	DBLP DOI BibTeX RDF
2	Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
2	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Systematic Scan Reconfiguration.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
2	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic Logic BIST for Transition Fault Testing.	European Test Symposium	2006	DBLP DOI BibTeX RDF	Deterministic logic BIST, delay test
2	Xijiang Lin, Janusz Rajski	The Impacts of Untestable Defects on Transition Fault Testing.	VTS	2006	DBLP DOI BibTeX RDF
2	Maria K. Michael, Stelios Neophytou, Spyros Tragoudas	Functions for Quality Transition Fault Tests.	ISQED	2005	DBLP DOI BibTeX RDF
2	V. R. Devanathan	Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic	At-Speed Transition Fault Testing With Low Speed Scan Enable.	VTS	2005	DBLP DOI BibTeX RDF
2	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Quality Transition Fault Tests Suitable for Small Delay Defects.	ICCD	2005	DBLP DOI BibTeX RDF
2	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Test set enhancement for quality transition faults using function-based methods.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high quality test, ATPG, delay test, critical paths, transition fault, test compaction
2	Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	stuck-at vectors, delay testing, transition fault
2	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
2	Gang-Min Park, Hoon Chang	An extended march test algorithm for embedded memories.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	efficient test algorithm, BIST architecture, neighborhood pattern sensitive fault, background data, word-oriented memory testing, extended march test algorithm, stuck-at fault, transition fault, embedded memories, integrated memory circuits, coupling fault
2	Niranjan L. Cooray, Edward W. Czeck	Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	sequential logic test generation, finite state machine testing, transition fault, distinguishing sequences
2	Kwang-Ting Cheng	Transition fault testing for sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
2	Michael H. Schultz, Franc Brglez	Accelerated Transition Fault Simulation.	DAC	1987	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity.	PRDC	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Diagnosis of transition fault clusters.	DAC	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Broadside tests, multicycle tests, fault diagnosis, transition faults
1	V. R. Devanathan, Ishaan Santhosh Shah	Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Yu Zhang, Vishwani D. Agrawal	Reduced complexity test generation algorithms for transition fault diagnosis.	ICCD	2011	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Zhen Chen, Dong Xiang	A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Manu Baby, Vijay Sarathi	Slack-based approach for peak power reduction during transition fault testing.	ISQED	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.	DDECS	2010	DBLP DOI BibTeX RDF
1	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
1	Tsuyoshi Iwagaki, Mineo Kaneko	A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties.	DELTA	2010	DBLP DOI BibTeX RDF	pseudo-Boolean model, all-output-propagation (AOP), test set reduction, transition fault
1	Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings	A Partially-Exhaustive Gate Transition Fault Model.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Zhen Chen, Dong Xiang, Boxue Yin	The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost.	VTS	2009	DBLP DOI BibTeX RDF
1	Jan Schat	On the relationship between stuck-at fault coverage and transition fault coverage.	DATE	2009	DBLP BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.	DFT	2009	DBLP DOI BibTeX RDF
1	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Zhanglei Wang, Hongxia Fang, Krishnendu Chakrabarty, Michael Bienek	Deviation-Based LFSR Reseeding for Test-Data Compression.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor	Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation.	DATE	2008	DBLP DOI BibTeX RDF
1	Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li	A Case Study on At-Speed Testing for a Gigahertz Microprocessor.	DELTA	2008	DBLP DOI BibTeX RDF	test power consumption, test coverage, at-speed testing, test time, test data volume
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Development of Functional Delay Tests.	DSD	2008	DBLP DOI BibTeX RDF
1	Jaekwang Lee, Intaik Park, Edward J. McCluskey	Error Sequence Analysis.	VTS	2008	DBLP DOI BibTeX RDF
1	Zheng Wang, D. M. H. Walker	Dynamic Compaction for High Quality Delay Test.	VTS	2008	DBLP DOI BibTeX RDF	dynamic compaction, test generation, delay test, path delay fault
1	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	On Complete Functional Broadside Tests for Transition Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Skewed-load, Scan division, At-speed test, Low-power test
1	Irith Pomeranz, Sudhakar M. Reddy	Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	High-Quality Transition Fault ATPG for Small Delay Defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler	Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic logic BIST for transition fault testing.	IET Computers & Digital Techniques	2007	DBLP BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo	Estimation of delay test quality and its application to test generation.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	The Criteria of Functional Delay Test Quality Assessment.	DSD	2007	DBLP DOI BibTeX RDF
1	Federico Baronti, Roberto Roncella, Roberto Saletti, Paolo D'Abramo, L. Di Piro, H. Fabian, M. Giardi	The importance of At-Speed Scan Testing: an industrial experience.	DSD	2007	DBLP DOI BibTeX RDF
1	Jian Kang, Sharad C. Seth, Vijay Gangaram	Efficient RTL Coverage Metric for Functional Test Selection.	VTS	2007	DBLP DOI BibTeX RDF
1	Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware	Silicon Evaluation of Static Alternative Fault Models.	VTS	2007	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda	Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich	Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.	ITC	2006	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A Framework of High-quality Transition Fault ATPG for Scan Circuits.	ITC	2006	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Transition Fault Test Reuse.	DSD	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Generation of broadside transition fault test sets that detect four-way bridging faults.	DATE	2006	DBLP DOI BibTeX RDF
1	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Timing-based delay test for screening small delay defects.	DAC	2006	DBLP DOI BibTeX RDF	test generation, delay testing
1	Irith Pomeranz, Sudhakar M. Reddy	A delay fault model for at-speed fault simulation and test generation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Sezer Gören, F. Joel Ferguson	Test sequence generation for controller verification and test with high coverage.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	finite state machine, Fault coverage, black box testing, X-machine
1	Irith Pomeranz, Sudhakar M. Reddy	Fault Collapsing for Transition Faults Using Extended Transition Faults.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Jais Abraham, Uday Goel, Arun Kumar	Multi-Cycle Sensitizable Transition Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Generation of Functional Broadside Tests for Transition Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Xiao Liu, Michael S. Hsiao	A Novel Transition Fault ATPG That Reduces Yield Loss.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	Hardware I Computing Methodologies
1	Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar	Enhanced launch-off-capture transition fault testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	Propagation delay fault: a new fault model to test delay faults.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour	Diagnosing multiple transition faults in the absence of timing information.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	diagnosis, multiple faults, delay faults, incremental, transition faults
1	Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman	Practical Aspects of Delay Testing for Nanometer Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	T. M. Mak	Limitation of structural scan delay test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Praveen Parvathala	High Level Test Generation / SW based Embedded Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Bhushan Vaidya, Mehdi Baradaran Tahoori	Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.	DFT	2005	DBLP DOI BibTeX RDF
1	Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey	Effective TARO Pattern Generation.	VTS	2005	DBLP DOI BibTeX RDF
1	Kai Yang, Kwang-Ting Cheng, Li-C. Wang	TranGen: a SAT-based ATPG for path-oriented transition faults.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng	Pattern Selection for Testing of Deep Sub-Micron Timing Defects. (PDF / PS)	DATE	2004	DBLP DOI BibTeX RDF
1	Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley	Low Overhead Delay Testing of ASICS.	ITC	2004	DBLP DOI BibTeX RDF
1	Puneet Gupta, Michael S. Hsiao	ALAPTF: A new Transition Faultmodel and the ATPG Algorithm.	ITC	2004	DBLP DOI BibTeX RDF
1	Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede	Systematic Defects in Deep Sub-Micron Technologies.	ITC	2004	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Interconnect Delay Testing of Designs on Programmable Logic Devices.	ITC	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger	Delay Defect Screening using Process Monitor Structures.	VTS	2004	DBLP DOI BibTeX RDF
1	Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li, D. M. H. Walker, Weiping Shi	A Statistical Fault Coverage Metric for Realistic Path Delay Faults.	VTS	2004	DBLP DOI BibTeX RDF
1	Xiao Liu, Michael S. Hsiao	Constrained ATPG for Broadside Transition Testing.	DFT	2003	DBLP DOI BibTeX RDF
1	Puneet Gupta, Michael S. Hsiao	High Quality ATPG for Delay Defects.	ITC	2003	DBLP DOI BibTeX RDF
1	Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.	ITC	2003	DBLP DOI BibTeX RDF
1	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Magdy S. Abadir, Juhong Zhu	Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs.	VTS	2003	DBLP DOI BibTeX RDF
1	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
1	Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech	Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .	ITC	2002	DBLP DOI BibTeX RDF
1	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Enhancing test efficiency for delay fault testing using multiple-clocked schemes.	DAC	2002	DBLP DOI BibTeX RDF	transition fault model, delay testing, statistical timing analysis