Search results for "transition faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
3	Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour	Diagnosing multiple transition faults in the absence of timing information.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	diagnosis, multiple faults, delay faults, incremental, transition faults
3	Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	On test generation for transition faults with minimized peak power dissipation.	DAC	2004	DBLP DOI BibTeX RDF	test generation, power dissipation, transition faults
2	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	On Complete Functional Broadside Tests for Transition Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.	VTS	2008	DBLP DOI BibTeX RDF	functional broadside tests, test generation, transition faults, reachable states, full-scan circuits
2	Irith Pomeranz, Sudhakar M. Reddy	Generation of Functional Broadside Tests for Transition Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Fault Collapsing for Transition Faults Using Extended Transition Faults.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.	VTS	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Test compaction for transition faults under transparent-scan.	DATE	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.	DFT	2006	DBLP DOI BibTeX RDF
2	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Test set enhancement for quality transition faults using function-based methods.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high quality test, ATPG, delay test, critical paths, transition fault, test compaction
2	Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
2	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	Scan BIST Targeting Transition Faults Using a Markov Source.	ISQED	2004	DBLP DOI BibTeX RDF
2	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
2	Gang Chen, Sudhakar M. Reddy, Irith Pomeranz	Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
2	Yun Shao 0002, Irith Pomeranz, Sudhakar M. Reddy	On Generating High Quality Tests for Transition Faults.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer	Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
2	Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel	On Double Transition Faults as a Delay Fault Model.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
2	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
1	Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo	Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Irith Pomeranz	Fast Identification of Undetectable Transition Faults under Functional Broadside Tests.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Undetectable transition faults under broadside tests with constant primary input vectors.	IET Computers & Digital Techniques	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Resolution of Diagnosis Based on Transition Faults.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Irith Pomeranz	Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults.	PRDC	2011	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja	On Detecting Transition Faults in the Presence of Clock Delay Faults.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	On clustering of undetectable transition faults in standard-scan circuits.	VTS	2011	DBLP DOI BibTeX RDF
1	Irith Pomeranz	On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Broadside tests, multicycle tests, fault diagnosis, transition faults
1	Irith Pomeranz, Sudhakar M. Reddy	Switching Activity as a Test Compaction Heuristic for Transition Faults.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
1	Irith Pomeranz, Sudhakar M. Reddy	Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Test compaction methods for transition faults under transparent-scan.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu	Diagnostic test generation for transition faults using a stuck-at ATPG tool.	ITC	2009	DBLP DOI BibTeX RDF
1	Dong Xiang, Boxue Yin, Kwang-Ting Cheng	Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure.	VTS	2009	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	State persistence: a property for guiding test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	broadside tests, test generation, transition faults, scan-based tests
1	Irith Pomeranz, Sudhakar M. Reddy	Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Zhanglei Wang, Hongxia Fang, Krishnendu Chakrabarty, Michael Bienek	Deviation-Based LFSR Reseeding for Test-Data Compression.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li	Layout-aware scan chain reorder for launch-off-shift transition test coverage.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scan chain ordering, test generation, transition faults, Scan test
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Development of Functional Delay Tests.	DSD	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Effectiveness of scan-based delay fault tests in diagnosis of transition faults.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Transition Faults Testing Based on Functional Delay Tests.	DDECS	2007	DBLP BibTeX RDF
1	Sying-Jyan Wang, Tung-Hua Yeh	High-level test synthesis for delay fault testability.	DATE	2007	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo	Estimation of delay test quality and its application to test generation.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Zhanglei Wang, Krishnendu Chakrabarty, Michael Bienek	A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Functional Broadside Tests with Different Levels of Reachability.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Lei Fang	RTL Test Point Insertion to Reduce Delay Test Volume.	VTS	2007	DBLP DOI BibTeX RDF
1	Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
1	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	High-Quality Transition Fault ATPG for Small Delay Defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Noriyuki Ito, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi	Delay defect screening for a 2.16GHz SPARC64 microprocessor.	ASP-DAC	2006	DBLP DOI BibTeX RDF	delay defect, microprocessor, screening, at-speed
1	Irith Pomeranz, Sudhakar M. Reddy	Generation of broadside transition fault test sets that detect four-way bridging faults.	DATE	2006	DBLP DOI BibTeX RDF
1	Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas	Transition Fault Test Reuse.	DSD	2006	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	The Impacts of Untestable Defects on Transition Fault Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Srikanth Venkataraman	An algorithmic technique for diagnosis of faulty scan chains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar	On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Bhushan Vaidya, Mehdi Baradaran Tahoori	Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.	DFT	2005	DBLP DOI BibTeX RDF
1	Maria K. Michael, Stelios Neophytou, Spyros Tragoudas	Functions for Quality Transition Fault Tests.	ISQED	2005	DBLP DOI BibTeX RDF
1	Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee	Transition Tests for High Performance Microprocessors.	VTS	2005	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan, Chunsheng Liu	EBIST: a novel test generator with built-in fault detection capability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Kai Yang, Kwang-Ting Cheng, Li-C. Wang	TranGen: a SAT-based ATPG for path-oriented transition faults.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Puneet Gupta, Michael S. Hsiao	ALAPTF: A new Transition Faultmodel and the ATPG Algorithm.	ITC	2004	DBLP DOI BibTeX RDF
1	Wangqi Qiu, Jing Wang 0006, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran	K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.	ITC	2004	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen	Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Shreyas Sundaram, Christoforos N. Hadjicostis	Non-concurrent Error Detection and Correction in Switched Linear Controllers.	HSCC	2004	DBLP DOI BibTeX RDF
1	Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara	BIST-oriented test pattern generator for detection of transition faults.	Systems and Computers in Japan	2003	DBLP DOI BibTeX RDF
1	Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu	Defect Oriented Fault Analysis for SRAM.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Xiao Liu, Michael S. Hsiao	Constrained ATPG for Broadside Transition Testing.	DFT	2003	DBLP DOI BibTeX RDF
1	Christoforos N. Hadjicostis	Encoded finite-state machines for non-concurrent error detection and identification.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Puneet Gupta, Michael S. Hsiao	High Quality ATPG for Delay Defects.	ITC	2003	DBLP DOI BibTeX RDF
1	Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.	ITC	2003	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Built-In Reseeding for Serial Bist.	VTS	2003	DBLP DOI BibTeX RDF
1	Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	stuck-at vectors, delay testing, transition fault
1	Irith Pomeranz, Sudhakar M. Reddy	On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.	ICCD	2002	DBLP DOI BibTeX RDF
1	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo	Application of High-Quality Built-In Test to Industrial Designs.	ITC	2002	DBLP DOI BibTeX RDF
1	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	MTDT	2002	DBLP DOI BibTeX RDF
1	Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu	An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.	PRDC	2002	DBLP DOI BibTeX RDF
1	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
1	Der-Cheng Huang, Wen-Ben Jone	A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Samrat Goswami, Anupam Chanda, D. Roy Choudhury	Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	Testing FSM, Single State Transition Fault Model, Sequential Machine
1	Irith Pomeranz, Sudhakar M. Reddy	On diagnosis and diagnostic test generation for pattern-dependenttransition faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Functional Test Generation for Full Scan Circuits.	DATE	2000	DBLP DOI BibTeX RDF
1	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
1	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sets and variable n-detection test sets fortransition faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik	Line coverage of path delay faults.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.	VTS	1999	DBLP DOI BibTeX RDF
1	Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar	Testing High Speed VLSI Devices Using Slower Testers.	VTS	1999	DBLP DOI BibTeX RDF
1	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR-a new test pattern generator for built-in-self-test.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
1	Irith Pomeranz, Sudhakar M. Reddy	On methods to match a test pattern generator to a circuit-under-test.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF