Search results for "translation lookaside buffer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2		Translation Lookaside Buffer (TLB).	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
2	Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim	A selective filter-bank TLB system.	ISLPED	2003	DBLP DOI BibTeX RDF	performance evaluation, translation lookaside buffer, low power consumption, filtering mechanism
2	Gokul B. Kandiraju, Anand Sivasubramaniam	Going the Distance for TLB Prefetching: An Application-Driven Study. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Application-driven Study, Simulation, Prefetching, Memory Hierarchy, Translation Lookaside Buffer
2	Qidong Xu, Patricia J. Teller	Unified vs. split TLBs and caches in shared-memory MP systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	data references, performance evaluation, caches, discrete event simulation, shared-memory multiprocessors, shared memory systems, trace-driven simulations, cache storage, performance gains, translation-lookaside buffer
2	Bryan S. Rosenburg	Low-Synchronization Translation Lookaside Buffer Consistency in Large-Scale Shared-Memory Multiprocessors.	SOSP	1989	DBLP DOI BibTeX RDF
2	David L. Black, Richard F. Rashid, David B. Golub, Charles R. Hill, Robert V. Baron	Translation Lookaside Buffer Consistency: A Software Approach.	ASPLOS	1989	DBLP DOI BibTeX RDF	UNIX
1	Girish Venkatasubramanian, Renato J. O. Figueiredo, Ramesh Illikkal	On the Performance of Tagged Translation Lookaside Buffers: A Simulation-Driven Analysis.	MASCOTS	2011	DBLP DOI BibTeX RDF	hardware-managed TLB, tagged TLB, virtualization, Translation lookaside buffer, full-system simulation
1	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
1	Thomas W. Barr, Alan L. Cox, Scott Rixner	Translation caching: skip, don't walk (the page table).	ISCA	2010	DBLP DOI BibTeX RDF	page walk caching, memory management, tlb
1	John Cieslewicz, Kenneth A. Ross	Data partitioning on chip multiprocessors.	DaMoN	2008	DBLP DOI BibTeX RDF
1	Mel Gorman, Patrick Healy	Supporting superpage allocation without additional hardware support.	ISMM	2008	DBLP DOI BibTeX RDF	superpage, fragmentation, replacement policy, tlb
1	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
1	Satoshi Yamada, Shigeru Kusakabe	Effect of context aware scheduler on TLB.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Xiantao Zhang, Anthony X. F. Xu, Qi Li, David K. Y. Yau, Sihan Qing, Huanguo Zhang	A hash-TLB approach for MMU virtualization in xen/IA64.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Rupak Samanta, Jason Surprise, Rabi N. Mahapatra	Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Reza Azimi, Livio Soares, Michael Stumm, Thomas Walsh, Angela Demke Brown	Path: page access tracking to improve memory management.	ISMM	2007	DBLP DOI BibTeX RDF	page access tracking, page re-, translation lookaside buffer
1	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Reducing Data TLB Power via Compiler-Directed Address Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Yen-Jen Chang, Maofeng Lan	Two New Techniques Integrated for Energy-Efficient TLB Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jinzhan Peng, Guei-Yuan Lueh, Gansha Wu, Xiaogang Gou, Ryan Rakvic	A comprehensive study of hardware/software approaches to improve TLB performance for java applications on embedded systems.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	TLB performance, Java, embedded system
1	Xiangrong Zhou, Peter Petrov	Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors.	CODES+ISSS	2005	DBLP DOI BibTeX RDF
1	Xiangrong Zhou, Peter Petrov	Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Steven Robbins	An address translation simulator.	SIGCSE	2005	DBLP DOI BibTeX RDF	operating systems, virtual memory, address translation
1	Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman	Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.	ISQED	2005	DBLP DOI BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
1	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Compiler-directed physical address generation for reducing dTLB power.	ISPASS	2004	DBLP DOI BibTeX RDF
1	Lawrence T. Clark, Byungwoo Choi, Michael Wilkerson	Reducing translation lookaside buffer active power.	ISLPED	2003	DBLP DOI BibTeX RDF	memory management units, low power, register files, translation lookaside buffers, dynamic circuits
1	Anthony S. Fong	A computer architecture with access control and cache option tags on individual instruction operands.	SIGARCH Computer Architecture News	2003	DBLP DOI BibTeX RDF	operand descriptor, optional encaching, system attributes, access control, data coherency
1	Peter Petrov, Alex Orailoglu	Virtual Page Tag Reduction for Low-power TLBs.	ICCD	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
1	Jung-Hoon Lee, Seh-Woong Jeong, Shin-Dug Kim, Charles C. Weems	A banked-promotion translation lookaside buffer system.	Journal of Systems Architecture	2002	DBLP DOI BibTeX RDF
1	Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen	Generating physical addresses directly for saving instruction TLB energy.	MICRO	2002	DBLP DOI BibTeX RDF
1	Yen-Jen Chang, Feipei Lai	Paged cache: an efficient partition architecture for reducing power, area and access time.	APCCAS	2002	DBLP DOI BibTeX RDF
1	Vincent Loechner, Benoît Meister, Philippe Clauss	Data Sequence Locality: A Generalization of Temporal Locality.	Euro-Par	2001	DBLP DOI BibTeX RDF	cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests
1	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
1	Naila Rahman, Richard Cole, Rajeev Raman	Optimised Predecessor Data Structures for Internal Memory.	Algorithm Engineering	2001	DBLP DOI BibTeX RDF
1	Siddhartha Chatterjee, Sandeep Sen	Cache-Efficient Matrix Transposition.	HPCA	2000	DBLP DOI BibTeX RDF
1	Xiaogang Qiu, Michel Dubois	Options for Dynamic Address Translation in COMAs.	ISCA	1998	DBLP DOI BibTeX RDF
1	John McCalpin, Mark Smotherman	Automatic benchmark generation for cache optimization of matrix operations.	ACM Southeast Regional Conference	1995	DBLP DOI BibTeX RDF
1	Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown	Design Tradeoffs for Software-Managed TLBs.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring
1	Madhusudhan Talluri, Mark D. Hill	Surpassing the TLB Performance of Superpages with Less Operating System Support.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	David F. Bacon, Jyh-Herng Chow, Dz-ching Ju, Kalyan Muthukumar, Vivek Sarkar	A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness.	CASCON	1994	DBLP DOI BibTeX RDF
1	Brian K. Bray, Michael J. Flynn	Translation hint buffers to reduce access time of physically-addressed instruction caches.	MICRO	1992	DBLP DOI BibTeX RDF	physical address, virtual address, cache, virtual memory, translation lookaside buffer
1	William J. Dally	A Fast Translation Method for Paging on top of Segmentation.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	fine grain relocation, one-step translation, virtual address, physical address, TLB reads, fine-grain protection, segmentation, object-oriented programming, paging, virtual storage, translation lookaside buffer
1	Patricia J. Teller	Translation-Lookaside Buffer Consistency.	IEEE Computer	1990	DBLP DOI BibTeX RDF
1	Andrew Braunstein, Mark Riley, John Wilkes	Improving the Efficiency of UNIX File Buffer Caches.	SOSP	1989	DBLP DOI BibTeX RDF	UNIX
1	Michael Y. Thompson, J. M. Barton, T. A. Jermoluk, J. C. Wagner	Translation Lookaside Buffer Synchronization in a Multiprocessor System.	USENIX Winter	1988	DBLP BibTeX RDF
1	Richard Mateosian	System considerations in the NS32032 design.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF