Search results for "ultra-low power applications"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Lu Chao, Chi-Ying Tsui, Wing-Hung Ki	Vibration energy scavenging and management for ultra low power applications.	ISLPED	2007	DBLP DOI BibTeX RDF	batteryless, energy scavenging and management, MPPT
2	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A nanowatt ADC for ultra low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Alexander Fish, Shy Hamami, Orly Yadid-Pecht	Self-powered active pixel sensors for ultra low-power applications.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Rohit Dhiman, Rajeevan Chandel	Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly	Vertical Slit Field Effect Transistor in ultra-low power applications.	ISQED	2012	DBLP DOI BibTeX RDF
1	Subhra Dhar, Manisha Pattanaik, Poolla Rajaram	Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard	40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Khawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar	Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling.	ISQED	2011	DBLP DOI BibTeX RDF
1	S. D. Pable, Mohd. Hasan	Performance analysis of FPGA interconnect fabric for ultra-low power applications.	ICCCS	2011	DBLP DOI BibTeX RDF
1	Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey	A low-leakage parallel CRC generator for ultra-low power applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ashutosh Nandi, Rajeevan Chandel	Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao	New SRAM design using body bias technique for ultra low power applications.	ISQED	2010	DBLP DOI BibTeX RDF
1	Mingoo Seok, David Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
1	Sumanth Amarchinta, Dhireesha Kudithipudi	Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	charge-boosters, subthreshold design, biasing
1	Yusuf Leblebici	Subthreshold Circuit Design for Ultra-Low-Power Applications.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.	ISLPED	2009	DBLP DOI BibTeX RDF	bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
1	Le Zheng, Hsin-Cheng Yao, Fred Tzeng, Payam Heydari	Design and Analysis of a Current-reuse Transmitter for Ultra-low Power Applications.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
1	Biswajit Mishra, Bashir M. Al-Hashimi	Subthreshold FIR Filter Architecture for Ultra Low Power Applications.	PATMOS	2008	DBLP DOI BibTeX RDF	Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR
1	Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer	Improving the power-delay product in SCL circuits using source follower output stage.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Jens-Peter Kaps	Chai-Tea, Cryptographic Hardware Implementations of xTEA.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	symmetric key algorithms, TEA, XTEA, FPGA, ASIC, Efficient implementation
1	Hamed F. Dadgour, Kaustav Banerjee	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
1	Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Vt balancing and device sizing towards high yield of sub-threshold static logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	variability, sub-threshold
1	Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw	Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.	DAC	2007	DBLP DOI BibTeX RDF
1	Vahid Moalemi, Ali Afzali-Kusha	Subthreshold Pass Transistor Logic for Ultra-Low Power Operation.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	S. Miller, Leonard MacEachern	A nanowatt bandgap voltage reference for ultra-low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Luis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije	Ultra low-voltage ultra low-power CMOS threshold voltage reference.	SBCCI	2006	DBLP DOI BibTeX RDF	low power, CMOS, low voltage, threshold voltage, voltage reference
1	Hui Shao, Chi-Ying Tsui, Wing-Hung Ki	A charge based computation system and control strategy for energy harvesting applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester	Analysis and mitigation of variability in subthreshold design.	ISLPED	2005	DBLP DOI BibTeX RDF	max of lognormal RVs, subthreshold variability
1	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
1	Jürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel	Power Supply Net for Adiabatic Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	G. Bonfini, C. Garbossa, Roberto Saletti	A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier	A hybrid adiabatic content addressable memory for ultra low-power applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	adiabatic switching, ultra-low power, energy recovery
1	R. Murali, Lihui Wang, Blanca Austin, James D. Meindl	Low-power circuit advantages of the scaled accumulation FET.	ISCAS	2002	DBLP DOI BibTeX RDF