Search results for "variable latency"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu	Collaborative voltage scaling with online STA and variable-latency datapath.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling
3	Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh	Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.	ISLPED	2007	DBLP DOI BibTeX RDF	variable-latency adder (VL-adder), negative bias temperature instability (NBTI)
3	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana	High-Level Synthesis with Variable-Latency Components.	VLSI Design	2000	DBLP DOI BibTeX RDF	variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
2	Daniel Piso Fernandez, Javier D. Bruguera	Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Goldschmidt algorithm, square root reciprocal, variable latency, division, square root, rounding, reciprocal
2	Ajay K. Verma, Philip Brisk, Paolo Ienne	Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.	DATE	2008	DBLP DOI BibTeX RDF
2	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
2	Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail	Variable latency caches for nanoscale processor.	SC	2007	DBLP DOI BibTeX RDF
2	Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska	An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.	DAC	2007	DBLP DOI BibTeX RDF
2	Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt	A Scalable Instruction Queue Design Using Dependence Chains. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Instruction Queue, Dependence Chains, Variable-latency, Scheduling, Scalable, Segment
2	Mauro Olivieri	Design of synchronous and asynchronous variable-latency pipelined multipliers.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Toshinori Sato, Itsujiro Arita	Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse.	Euro-Par	2001	DBLP DOI BibTeX RDF
2	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana	Integrating variable-latency components into high-level synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Saket Gupta, Sachin S. Sapatnekar	BTI-aware design using variable latency units.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Kai Du, Peter J. Varman, Kartik Mohanram	High performance reliable variable latency carry select addition.	DATE	2012	DBLP BibTeX RDF
1	Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Performance Optimization Using Variable-Latency Design Style.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Mario R. Casu, Stefano Colazzo, Paolo Mantovani	Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Kai Du, Peter J. Varman, Kartik Mohanram	Static window addition: A new paradigm for the design of variable latency adders.	ICCD	2011	DBLP DOI BibTeX RDF
1	Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang	Variable-Latency Floating-Point Multipliers for Low-Power Applications.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang	Design methodology of variable latency adders with multistage function speculation.	ISQED	2010	DBLP DOI BibTeX RDF
1	J. Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo	Simulating a LAGS processor to consider variable latency on L1 D-Cache.	SummerSim	2010	DBLP BibTeX RDF
1	Xiaoyao Liang, Gu-Yeon Wei, David Brooks	Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Daniel Piso Fernandez, Javier D. Bruguera	Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation.	DSD	2009	DBLP DOI BibTeX RDF
1	Alexandru Amaricai, Oana Boncalo	Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation.	DSD	2009	DBLP DOI BibTeX RDF
1	David Bañeres, Jordi Cortadella, Michael Kishinevsky	Variable-latency design by function speculation.	DATE	2009	DBLP BibTeX RDF
1	Rajiv T. Maheswaran, Craig Milo Rogers, Romeo Sanchez, Pedro A. Szekely, Gergely Gati, Kevin Smyth, Chris VanBuskirk	Multi-agent systems for the real world.	AAMAS	2009	DBLP DOI BibTeX RDF
1	Niranjan Suri	Dynamic service-oriented architectures for tactical edge networks.	WEWST	2009	DBLP DOI BibTeX RDF	dynamic service-oriented architectures, tactical edge networks, load balancing, service discovery, green computing, service migration
1	Dong Zhou, Ajay Chander, Hiroshi Inamura	Optimizing user interaction for mobile web browsing.	Mobile HCI	2009	DBLP DOI BibTeX RDF
1	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
1	Muhammad Umar Farooq, Lizy K. John	Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures.	CC	2009	DBLP DOI BibTeX RDF	tiled dataflow architectures, operand network latency, instruction scheduling, resource contention
1	Xiaoyao Liang, Gu-Yeon Wei, David Brooks	ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.	ISCA	2008	DBLP DOI BibTeX RDF
1	Daniel Piso Fernandez, Javier D. Bruguera	A New Rounding Algorithm for Variable Latency Division and Square Root Implementations.	DSD	2008	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Kaushik Roy	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Eric Chun, Zeshan Chishti, T. N. Vijaykumar	Shapeshifter: Dynamically changing pipeline width and speed to address process variations.	MICRO	2008	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy	Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems.	CGO	2007	DBLP DOI BibTeX RDF
1	Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte	Hardware design of a Binary Integer Decimal-based floating-point adder.	ICCD	2007	DBLP DOI BibTeX RDF
1	Roger S. Barga, Gueorgui Chkodrov	Coping with Variable Latency and Disorder in Distributed Event Streams.	ICDCS Workshops	2006	DBLP DOI BibTeX RDF
1	Jason P. Luck, Patricia L. McDermott, Laurel Allender, Deborah C. Russell	An investigation of real world control of robotic assets under communication latency.	HRI	2006	DBLP DOI BibTeX RDF	control and level of automation, communication, robotics, delay, latency, teleoperation
1	Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky	Performance analysis of concurrent systems with early evaluation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi	Architecture - The potential energy efficiency of vector acceleration.	SC	2006	DBLP DOI BibTeX RDF
1	Viay Holimath, Javier D. Bruguera	A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table.	DSD	2006	DBLP DOI BibTeX RDF
1	Matt J. Harvey, Shantenu Jha, Mary-Ann Thyveetil, Peter V. Coveney	Using Lambda Networks to Enhance Performance of Interactive Large Simulations.	e-Science	2006	DBLP DOI BibTeX RDF	lambda networks, NISTNet, visualisation, supercomputers, molecular dynamics, performance monitoring, Interactive simulations, lightpaths
1	Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz	High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
1	Humaira Kamal, Brad Penoff, Mike Tsai, E. Vong, Alan Wagner	Using SCTP to hide latency in MPI programs.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou	Yield-Aware Cache Architectures.	MICRO	2006	DBLP DOI BibTeX RDF
1	Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein	Hardware compilation of application-specific memory-access interconnect.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Sven Beyer, Christian Jacobi 0002, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul	Putting it all together - Formal verification of the VAMP.	STTT	2006	DBLP DOI BibTeX RDF	Complete microprocessor verification, Tomasulo scheduler, Cache memory interface, Model checking, Formal methods, Theorem proving, Floating point unit
1	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard	SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	high-level synthesis, memory synthesis
1	Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu	"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense.	MICRO	2005	DBLP DOI BibTeX RDF
1	Amélie Marian, Nicolas Bruno, Luis Gravano	Evaluating top-k queries over web-accessible databases.	ACM Trans. Database Syst.	2004	DBLP DOI BibTeX RDF	query optimization, web databases, Parallel query processing, top-k query processing
1	Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August	Decoupled Software Pipelining with the Synchronization Array.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Toshinori Sato, Itsujiro Arita	Combining variable latency pipeline with instruction reuse for execution latency reduction.	Systems and Computers in Japan	2003	DBLP DOI BibTeX RDF
1	Sudarshan K. Srinivasan, Miroslav N. Velev	Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions.	MEMOCODE	2003	DBLP DOI BibTeX RDF
1	Sven Beyer, Christian Jacobi 0002, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul	Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.	CHARME	2003	DBLP DOI BibTeX RDF
1	Christian Jacobi 0002	Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving.	CAV	2002	DBLP DOI BibTeX RDF
1	Mauro Olivieri	Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers".	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Silvia M. Müller	On the Scheduling of Variable Latency Functional Units.	SPAA	1999	DBLP DOI BibTeX RDF
1	Silvia M. Müller	A Hardware Scheduler for Controlling Variable Latency Functional Units.	Applied Informatics	1999	DBLP BibTeX RDF
1	Gianluca Cornetta, Jordi Cortadella	A Radix-16 SRT Division Unit with Speculation of the Quotient Digits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Patricia Borensztejn, Cristina Barrado, Jesús Labarta	Influence of Variable Time Operations in Static Instruction Scheduling.	Euro-Par	1999	DBLP DOI BibTeX RDF
1	Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino	Timed Supersetting and the Synthesis of Telescopic Units.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Pipelined Design, Logic Synthesis, Timing Analysis
1	Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli	Telescopic units: a new paradigm for performance optimization of VLSI designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Stuart F. Oberman, Michael J. Flynn	Division Algorithms and Implementations.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	functional iteration, variable latency, very high radix, Computer arithmetic, floating point, division, table look-up, SRT
1	Luca Benini, Enrico Macii, Massimo Poncino	Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.	DAC	1997	DBLP DOI BibTeX RDF
1	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
1	Stuart F. Oberman, Michael J. Flynn	A Variable Latency Pipelined Floating-Point Adder.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF