Search results for "variation aware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Tarek A. El-Moselhy, Luca Daniel	Stochastic dominant singular vectors method for variation-aware extraction.	DAC	2010	DBLP DOI BibTeX RDF	intrusive algorithms, stochastic PDEs, stochastic dominant singular vectors, variation-aware extraction, stochastic simulation, integral equations, surface roughness, parasitic extraction
3	Gregory Lucas, Chen Dong, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
3	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.	ISLPED	2009	DBLP DOI BibTeX RDF	significance driven computation, variation aware, voltage over-scaling, low power, motion estimation
3	Seyed-Abdollah Aftabjahani, Linda S. Milor	Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis
2	Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun	Power-efficient variation-aware photonic on-chip network management.	ISLPED	2010	DBLP DOI BibTeX RDF	networks on chip, optical interconnects, nanophotonics
2	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
2	Xiaoming Chen, Yu Wang 0002, Yu Cao, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
2	HaNeul Chon, Taewhan Kim	Timing variation-aware task scheduling and binding for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Gregory Lucas, Scott Cromar, Deming Chen	FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Yuan Xie, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Chen Dong, Scott Chilstedt, Deming Chen	FPCNA: a field programmable carbon nanotube array.	FPGA	2009	DBLP DOI BibTeX RDF	cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
2	Siddharth Garg, Diana Marculescu	System-level throughput analysis for process variation aware multiple voltage-frequency island designs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous
2	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	TRETS	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
2	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
2	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
2	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
2	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
2	Tarek Moselhy, Luca Daniel	Stochastic integral equation solver for efficient variation-aware interconnect extraction.	DAC	2008	DBLP DOI BibTeX RDF	Neumann expansion, polynomial chaos expansion, stochastic field solvers, variation-aware extraction, surface roughness
2	Raghavendra K, Madhu Mutyam	Process Variation Aware Issue Queue Design.	DATE	2008	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Guangyu Sun, Yuan Xie	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
2	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
2	Venkataraman Mahalingam, N. Ranganathan	Variation Aware Timing Based Placement Using Fuzzy Programming.	ISQED	2007	DBLP DOI BibTeX RDF
2	Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy	A process variation aware low power synthesis methodology for fixed-point FIR filters.	ISLPED	2007	DBLP DOI BibTeX RDF	fixed-point FIR filters, variation aware, low-power, synthesis
2	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
2	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
2	Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah	Variation-aware performance verification using at-speed structural test and statistical timing.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Suresh Srinivasan, Narayanan Vijaykrishnan	Variation Aware Placement for FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III	A novel approach for variation aware power minimization during gate sizing.	ISLPED	2006	DBLP DOI BibTeX RDF
2	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
2	Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira	Variation-Aware, Library Compatible Delay Modeling Strategy.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Peng Yu, Sean X. Shi, David Z. Pan	Process variation aware OPC with variational lithography modeling.	DAC	2006	DBLP DOI BibTeX RDF	lithography modeling, process variation, OPC
2	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
2	Rasit Onur Topaloglu, Alex Orailoglu	A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.	DAC	2005	DBLP DOI BibTeX RDF
2	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Saumya Chandra, Anand Raghunathan, Sujit Dey	Variation-Aware Voltage Level Selection.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Satyajit Desai, Sanghamitra Roy, Koushik Chakraborty	Process variation aware DRAM design using block based adaptive body biasing algorithm.	ISQED	2012	DBLP DOI BibTeX RDF
1	Davit Mirzoyan, Benny Akesson, Kees Goossens	Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield.	ISQED	2012	DBLP DOI BibTeX RDF
1	Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi Kudahi	History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.	ISQED	2012	DBLP DOI BibTeX RDF
1	Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich	Variation-aware leakage power model extraction for system-level hierarchical power analysis.	DATE	2012	DBLP BibTeX RDF
1	Yuanzhe Xu, Wenjian Yu, Quan Chen, Lijun Jiang, Ngai Wong	Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC.	DATE	2012	DBLP BibTeX RDF
1	Dimilri De Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos	Advances in variation-aware modeling, verification, and testing of analog ICs.	DATE	2012	DBLP BibTeX RDF
1	Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski	A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	John Rieffel	Trent McConaghy, P. Palmers, G. Peng, Michiel Steyaert, Georges Gielen: Variation-aware analog structural synthesis: a computational intelligence approach - Springer, 2009, ISBN 978-90-481-2905-8.	Genetic Programming and Evolvable Machines	2011	DBLP DOI BibTeX RDF
1	Kartikey Mittal, Arpit Joshi, Madhu Mutyam	Timing variation-aware scheduling and resource binding in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich	Variation-aware fault modeling.	SCIENCE CHINA Information Sciences	2011	DBLP DOI BibTeX RDF
1	Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-Aware Task and Communication Mapping for MPSoC Architecture.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Bo Liu, Francisco V. Fernández, Georges G. E. Gielen	Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi	A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Sudhakar S. Mande, Saurabh A. Chandorkar, A. N. Chandorkar	Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Upavan Gupta, Nagarajan Ranganathan	A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Enric Musoll	Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processors.	Computers & Electrical Engineering	2011	DBLP DOI BibTeX RDF
1	Tarek A. El-Moselhy, Luca Daniel	Variation-aware stochastic extraction with large parameter dimensionality: Review and comparison of state of the art intrusive and non-intrusive techniques.	ISQED	2011	DBLP DOI BibTeX RDF
1	Shahin Golshan, Love Singhal, Eli Bozorgzadeh	Process variation aware system-level load assignment for total energy minimization using stochastic ordering.	ISQED	2011	DBLP DOI BibTeX RDF
1	Urban Ingelsson, Bashir M. Al-Hashimi	Investigation into voltage and process variation-aware manufacturing test.	ITC	2011	DBLP DOI BibTeX RDF
1	Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim	Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David Blaauw, Dennis Sylvester	Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.	ISLPED	2011	DBLP BibTeX RDF
1	Mahmoud Momtazpour, Mahboobeh Ghorbani, Maziar Goudarzi, Esmaeil Sanaei	Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Akbar Sharifi, Mahmut T. Kandemir	Process variation-aware routing in NoC based multicores.	DAC	2011	DBLP DOI BibTeX RDF
1	Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell	Towards Variation-Aware Test Methods.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Delay test, Adaptive test, Parameter variations
1	Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara	Temperature-Variation-Aware Test Pattern Optimization.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Masoud Zamani, Mehdi Baradaran Tahoori	Variation-aware logic mapping for crossbar nano-architectures.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Ting Zhu, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon	Application of Surrogate Modeling in Variation-aware Macromodel and Circuit Design.	SIMULTECH	2011	DBLP BibTeX RDF
1	S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski	Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Mohammad Ghasemazar, Massoud Pedram	Variation aware dynamic power management for chip multiprocessor architectures.	DATE	2011	DBLP BibTeX RDF
1	Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram	Timing variation-aware custom instruction extension technique.	DATE	2011	DBLP DOI BibTeX RDF
1	Yuanzhe Xu, Quan Chen, Lijun Jiang, Ngai Wong	Process-variation-aware electromagnetic-semiconductor coupled simulation.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Martin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel	A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring.	DDECS	2011	DBLP DOI BibTeX RDF
1	Di-an Li, Malgorzata Marek-Sadowska	Variation-aware electromigration analysis of power/ground networks.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Sreeharsha Tavva, Dhireesha Kudithipudi	Characterization of Variation Aware Nanoscale Static Random Access Memory Designs.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Mahmoud Momtazpour, Maziar Goudarzi, Esmaeil Sanaei	Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Mohsen Raji, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi	Process variation-aware performance analysis of asynchronous circuits.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Gregory Lucas, Chen Dong, Deming Chen	Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Luís Guerra e Silva, Joel R. Phillips, Luis Miguel Silveira	Effective Corner-Based Techniques for Variation-Aware IC Timing Verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	HaNeul Chon, Taewhan Kim	Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC.	Comput. J.	2010	DBLP DOI BibTeX RDF
1	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Variation-Aware System-Level Power Analysis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Vee Kin Wong, Siong Kiong Teng	Variation aware guard -banding for SOC static timing analysis.	ISQED	2010	DBLP DOI BibTeX RDF
1	John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta	Variation-aware speed binning of multi-core processors.	ISQED	2010	DBLP DOI BibTeX RDF
1	Tayyeb Mahmood, Soontae Kim	Fine-Grained Fault Tolerance for Process Variation-Aware Caches.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto	0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.	ISLPED	2010	DBLP DOI BibTeX RDF	fine-grain control, low power, cache memory, microarchitecture, variation, low voltage
1	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
1	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
1	Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich	Variation-Aware Fault Modeling.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman	Timing-driven variation-aware nonuniform clock mesh synthesis.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clock mesh synthesis, non-tree clock networks, vlsi cad, power, process variations, physical design, clock skew, clock distribution
1	Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun	Improving SRAM Vmin and yield by using variation-aware BTI stress.	CICC	2010	DBLP DOI BibTeX RDF
1	Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar	Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Assem A. M. Bsoul, Naraig Manjikian, Li Shang	Reliability- and process variation-aware placement for FPGAs.	DATE	2010	DBLP BibTeX RDF
1	Tarek A. El-Moselhy, Luca Daniel	Variation-aware interconnect extraction using statistical moment preserving model order reduction.	DATE	2010	DBLP BibTeX RDF
1	Kiarash Amiri, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi	Process variation aware transcoding for low power H.264 decoding.	ESTImedia	2010	DBLP DOI BibTeX RDF
1	Siddharth Garg, Diana Marculescu, Sebastian Herbert	Process variation aware performance modeling and dynamic power management for multi-core systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Gregory Lucas, Deming Chen	Variation-aware layout-driven scheduling for performance yield optimization.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy	VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.	ICCD	2010	DBLP DOI BibTeX RDF
1	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
1	Lin Huang, Qiang Xu	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
1	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
1	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
1	Enric Musoll	A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF