Search results for "vector processing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Kai Hwang, Zhiwei Xu	Multipipeline Networking for Compound Vector Processing.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	compound vector processing, multipipeline networking, pipeline chaining, pipeline nets, run-time techniques, Livermore loops, performance evaluation, performance analysis, parallel programming, compilation, parallel architectures, programming, program compilers, pipeline processing, scientific programs, vector-processing, systolization
3	Jean-Pierre Banâtre, Michel Banâtre	Parallel structures for vector processing.	CONPAR	1981	DBLP DOI BibTeX RDF	Parallel Processing, Parallel Programming, Language Design, Vector Processing
2	Ai-Mei Huang, Truong Nguyen	Correlation-Based Motion Vector Processing With Adaptive Interpolation Scheme for Motion-Compensated Frame Interpolation.	IEEE Transactions on Image Processing	2009	DBLP DOI BibTeX RDF
2	Ai-Mei Huang, Truong Q. Nguyen	A Multistage Motion Vector Processing Method for Motion-Compensated Frame Interpolation.	IEEE Transactions on Image Processing	2008	DBLP DOI BibTeX RDF
2	Ai-Mei Huang, Truong Nguyen	Correlation-based motion vector processing for motion compensated frame interpolation.	ICIP	2008	DBLP DOI BibTeX RDF
2	Gokce Dane, Yan Ye, Yen-Chi Lee	Low-complexity temporal error concealment by motion vector processing for mobile video applications.	ICIP	2008	DBLP DOI BibTeX RDF
2	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
2	Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu	Vector Processing Support for FPGA-Oriented High Performance Applications.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Ai-Mei Huang, Truong Nguyen	A Novel Multi-Stage Motion Vector Processing Method for Motion Compensated Frame Interpolation.	ICIP	2007	DBLP DOI BibTeX RDF
2	Ai-Mei Huang, Truong Nguyen	Motion Vector Processing Based on Residual Energy Information for Motion Compensated Frame Interpolation.	ICIP	2006	DBLP DOI BibTeX RDF
2	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Franco Gasperoni	Vector Processing in Ada.	Ada-Europe	2004	DBLP DOI BibTeX RDF
2	Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li	An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing.	ICCD	2004	DBLP DOI BibTeX RDF
2	Tong Sun, Qing Yang	A Comparative Analysis of Cache Designs for Vector Processing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	simulation, Performance evaluation, benchmarks, memory hierarchy, cache memories, vector processing
2	Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa	A superscalar RISC processor with pseudo vector processing feature. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
2	Damianos G. Karakos, Panos E. Trahanias	Combining vector median and vector directional filters: the directional-distance filters. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	vector directional filters, multispectral image processing, directional-distance filters, vector approach, vector processing filters, MLE estimates, color image data processing, directional information, chromaticity preservation, image processing, noise, maximum likelihood estimation, spectral analysis, filtering theory, image colour analysis, median filters, exponential distribution, exponential distributions, vector median filters, impulsive noise removal
2	Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita	A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
2	Kei Hiraki, Satoshi Sekiguchi, Toshio Shimada	Efficient vector processing on dataflow supercomputer SIGMA-1.	SC	1988	DBLP BibTeX RDF
2	Kai Hwang, Lionel M. Ni	Resource Optimization of a Parallel Computer for Multiple Vector Processing.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	M/M/k/l queueing system, multiple SIMD (MSIMD) computer, parallel vector processing, performance optimization, multiprocessor architecture
1	Ye Gao, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi	An out-of-order vector processing mechanism for multimedia applications.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
1	Ju Hyun Park, Young-Chul Kim, Hong-Sung Hoon	Edge-Based Motion Vector Processing for Frame Interpolation Based on Weighted Vector Median Filter.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Thomas Willhalm, Nicolae Popovici, Yazan Boshmaf, Hasso Plattner, Alexander Zeier, Jan Schaffner	SIMD-Scan: Ultra Fast in-Memory Table Scan using on-Chip Vector Processing Units.	PVLDB	2009	DBLP BibTeX RDF
1	Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux	Vector Processing as a Soft Processor Accelerator.	TRETS	2009	DBLP DOI BibTeX RDF	parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
1	Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Ai-Mei Huang, Truong Nguyen	Motion vector processing based on trajectory curve analysis for motion compensated frame interpolation.	ICIP	2009	DBLP DOI BibTeX RDF
1	Ai-Mei Huang, Truong Nguyen	Motion vector processing using the color information.	ICIP	2009	DBLP DOI BibTeX RDF
1	Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella	Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing.	DATE	2009	DBLP BibTeX RDF
1	Deng Hui-Ping, Yu Li, Xiong Wei, He Qing-Di, Li Rong	Adaptive Interpolation/Extrapolation and Motion Vector Processing Method for Frame Rate Up Conversion.	ICIG	2009	DBLP DOI BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Fine-grain performance scaling of soft vector processors.	CASES	2009	DBLP DOI BibTeX RDF	VESPA, soft vector processor, viram, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Snaider Carrillo, Jakob Siegel, Xiaoming Li	A control-structure splitting optimization for GPGPU.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	optimizations, gpgpu, cuda
1	Praveen Kumar, Kannappan Palaniappan, Ankush Mittal, Guna Seetharaman	Parallel Blob Extraction Using the Multi-core Cell Processor.	ACIVS	2009	DBLP DOI BibTeX RDF
1	Ai-Mei Huang, Truong Nguyen	Motion vector processing using bidirectional frame difference in motion compensated frame interpolation.	WOWMOM	2008	DBLP DOI BibTeX RDF
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	VESPA: portable, scalable, and flexible FPGA-based vector processors.	CASES	2008	DBLP DOI BibTeX RDF	SPREE, VESPA, VIRAM, FPGA, custom, SIMD, vector, ASIP, microarchitecture, application specific, soft processor
1	Ashwin M. Aji, Wu-chun Feng, Filip Blagojevic, Dimitrios S. Nikolopoulos	Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	wavefront algorithms, cell broadband engine, smith-waterman
1	Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, André Bourdoux, David Novo, Liesbet Van der Perre, Francky Catthoor	Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.	ICC	2008	DBLP DOI BibTeX RDF
1	Tim Sweeney	Wild speculation on consumer workloads in 2010-2020.	IISWC	2008	DBLP DOI BibTeX RDF
1	Krzysztof Sierszecki, Christo Angelov, Xu Ke	A Run-Time Environment Supporting Real-Time Execution of Embedded Control Applications.	RTCSA	2008	DBLP DOI BibTeX RDF
1	Claire Fautsch, Ljiljana Dolamic, Jacques Savoy	UniNE at Domain-Specific IR - CLEF 2008.	CLEF	2008	DBLP DOI BibTeX RDF
1	Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu	FPGA-based Vector Processing for Matrix Operations.	ITNG	2007	DBLP DOI BibTeX RDF
1	Kenneth L. Holladay, Kay Robbins, Jeffery von Ronne	FIFTHTM: A Stack Based GP Language for Vector Processing.	EuroGP	2007	DBLP DOI BibTeX RDF	linear GP, GP environment, Genetic Programming, vectors
1	Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
1	Yunquan Zhang, Ying Chen, Yuan Tang	Block size selection of parallel LU and QR on PVP-based and RISC-based supercomputers.	China HPC	2007	DBLP DOI BibTeX RDF	LU, PVP, optimal parallel block size, RISC, ScaLAPACK, QR
1	Micha Nelissen, Kees van Berkel, Sergei Sawitzki	Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance.	FPL	2007	DBLP DOI BibTeX RDF
1	Robert A. Tefft, Roger Y. Lee	Reduction of Complexity and Automation of Parallel Execution through Loop Level Parallelism.	QSIC	2007	DBLP DOI BibTeX RDF
1	John T. Rickard, Ronald R. Yager	Hypercube Graph Representations and Fuzzy Measures of Graph Properties.	IEEE T. Fuzzy Systems	2007	DBLP DOI BibTeX RDF
1	Nicolas Fritz, Philipp Lucas, Reinhard Wilhelm	Exploiting SIMD Parallelism with the CGiSCompiler Framework.	LCPC	2007	DBLP DOI BibTeX RDF
1	Michael Freeman	Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors.	DSD	2006	DBLP DOI BibTeX RDF
1	Ben Weiss	Fast median and bilateral filtering.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	rank-order filtering, algorithms, image processing, complexity, data structures, sorting, SIMD, histograms, median filtering, bilateral filtering, vector processing
1	Vipin Sachdeva, Michael Kistler, Evan Speight	Poster reception - Pairwise alignments on the cell processor.	SC	2006	DBLP DOI BibTeX RDF
1	Steve Scott	Roadmaps and visions I - Cray: creating a path to adaptive supercomputing.	SC	2006	DBLP DOI BibTeX RDF
1	Liang Wang 0002, Miao Liao, Minglun Gong, Ruigang Yang, David Nistér	High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming.	3DPVT	2006	DBLP DOI BibTeX RDF
1	Pedro C. Diniz, Gokul Govindu	Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.	FPL	2006	DBLP DOI BibTeX RDF
1	Jacques Savoy, Samir Abdou	Experiments with Monolingual, Bilingual, and Robust Retrieval.	CLEF	2006	DBLP DOI BibTeX RDF
1	Kees van Berkel, Frank Heinle, Patrick P. E. Meuwissen, Kees Moerman, Matthias Weiss	Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices.	EURASIP J. Adv. Sig. Proc.	2005	DBLP DOI BibTeX RDF
1	Robert A. Brown, Hongmei Zhu, J. Ross Mitchell	Distributed vector Processing of a new local MultiScale Fourier transform for medical imaging applications.	IEEE Trans. Med. Imaging	2005	DBLP DOI BibTeX RDF
1	Reza Farivar, Mahdi Fazeli, Hamid Sarbazi-Azad	A Cordic-Based Processor Extension for Scalar and Vector Processing.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Muhammad Z. Hasan, Sotirios G. Ziavras	FPGA-Based Vector Processing for Solving Sparse Sets of Equations.	FCCM	2005	DBLP DOI BibTeX RDF
1	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
1	Jongmyon Kim, D. Scott Wills, Linda M. Wills	Architectural Enhancements for Color Image and Video Processing on Embedded Systems.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Jacques Savoy, Pierre-Yves Berger	Monolingual, Bilingual, and GIRT Information Retrieval at CLEF-2005.	CLEF	2005	DBLP DOI BibTeX RDF
1	Jacques J. A. Fournier, Simon W. Moore	A Vector Approach to Cryptography Implementation.	DRMTICS	2005	DBLP DOI BibTeX RDF	Cryptography, AES, RSA, vector architecture, Montgomery Modular Multiplication
1	Fumihiko Ino, Manabu Matsui, Keigo Goda, Kenichi Hagihara	Performance Study of LU Decomposition on the Programmable GPU.	HiPC	2005	DBLP DOI BibTeX RDF
1	Hossein Ahmadi, Maryam Moslemi Naeini, Hamid Sarbazi-Azad	Efficient SIMD Numerical Interpolation.	HPCC	2005	DBLP DOI BibTeX RDF
1	Akihito Takahashi, Stanislav Sedukhin	Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor.	HPCC	2005	DBLP DOI BibTeX RDF
1	Sadaf R. Alam, Jeffrey S. Vetter	Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization.	International Conference on Computational Science	2005	DBLP DOI BibTeX RDF
1	Bryson R. Payne, Saeid Belkasim, G. Scott Owen, Michael Weeks, Ying Zhu	Accelerated 2D Image Processing on GPUs.	International Conference on Computational Science	2005	DBLP DOI BibTeX RDF
1	Bryson R. Payne, G. Scott Owen, Irene Weber	Accelerating Protein Structure Recovery Using Graphics Processing Units.	International Conference on Computational Science	2005	DBLP DOI BibTeX RDF
1	Rodrigo de Luis García, Rachid Deriche, Mikaël Rousson, Carlos Alberola-López	Tensor Processing for Texture and Colour Segmentation.	SCIA	2005	DBLP DOI BibTeX RDF
1	Jung L. Lee, Myung Hoon Sunwoo	Implementation of a Wireless Multimedia DSP Chip for Mobile Applications.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	multimedia, DSP, instruction
1	Hongzhang Shan, Erich Strohmaier	Performance characteristics of the Cray X1 and their implications for application performance tuning.	ICS	2004	DBLP DOI BibTeX RDF	performance measurement, performance optimization, vector processing, performance characterization
1	Christian Bell, Wei-Yu Chen, Dan Bonachea, Katherine A. Yelick	Evaluating support for global address space languages on the Cray X1.	ICS	2004	DBLP DOI BibTeX RDF	X1, UPC, global address space
1	Ed Upchurch, Thomas L. Sterling, Jay B. Brockman	Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs.	SC	2004	DBLP DOI BibTeX RDF
1	Naga K. Govindaraju, Brandon Lloyd, Wei Wang 0010, Ming C. Lin, Dinesh Manocha	Fast Computation of Database Operations using Graphics Processors.	SIGMOD Conference	2004	DBLP DOI BibTeX RDF	selection query, selectivity analysis, semi-linear query, query optimization, aggregation, graphics processor
1	Andrew A. Gray, Scott D. Hoy, Parminder Ghuman	Adaptive LMS processing architectures employing frequency domain sub-convolution.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Sandeep Koranne	A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform.	ISQED	2004	DBLP DOI BibTeX RDF
1	Michael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis	A Low-Power Multithreaded Processor for Baseband Communication Systems.	SAMOS	2004	DBLP DOI BibTeX RDF
1	Christian Tenllado, Carlos García, Manuel Prieto, Luis Piñuel, Francisco Tirado	Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.	VECPAR	2004	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Fabrizio Lombardi	ATE-Amenable Test Data Compression with No Cyclic Scan.	DFT	2003	DBLP DOI BibTeX RDF
1	Sourav Chatterji, Manikandan Narayanan, Jason Duell, Leonid Oliker	Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine.	IPDPS	2003	DBLP DOI BibTeX RDF	multimedia applications, stream processing, QR decomposition, processor-in-memory, vector architecture
1	Andrew A. Gray	Parallel sub-convolution filter bank architectures.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yusaku Yamamoto, Mitsuyoshi Igai, Ken Naono	A Vector-Parallel FFT with a User-Specificable Data Distribution Scheme.	ISPA	2003	DBLP DOI BibTeX RDF
1	Adam Smyk, Marek Tudruj	Irregular Fine-Grain Parallel Computing Based on the Slide Register Window Architecture of Hitachi SR2201.	PARELEC	2002	DBLP DOI BibTeX RDF
1	Daisuke Takahashi, Mitsuhisa Sato, Taisuke Boku	Performance Evaluation of the Hitachi SR8000 Using OpenMP Benchmarks.	ISHPC	2002	DBLP BibTeX RDF
1	Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi	Vector processing of wavelet coefficients for robust image denoising.	Image Vision Comput.	2001	DBLP DOI BibTeX RDF
1	Ahmed El-Mahdy, Ian Watson	A Two Dimensional Vector Architecture for Multimedia.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Naraig Manjikian	A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication.	ASAP	2000	DBLP DOI BibTeX RDF	parallel processing, spread-spectrum communication, vector processing, multi-user detection
1	Samuel Larsen, Saman P. Amarasinghe	Exploiting superword level parallelism with multimedia instruction sets.	PLDI	2000	DBLP DOI BibTeX RDF
1	Lucas Szajek, Lev Kirischian	Implementation of an Adaptive Reconfigurable Group Organized (ARGO) Parallel Architecture.	PARELEC	2000	DBLP DOI BibTeX RDF
1	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
1	Hiroyasu Nishiyama, Keiko Motokawa, Ichiro Kyushima, Sumio Kikuchi	Pseudo-vectorizing Compiler for the SR8000 (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
1	David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David Martin, David A. Patterson	Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Seiji Nishimura, Daisuke Takahashi, Takaomi Shigehara, Hiroshi Mizoguchi, Taketoshi Mishima	A Performance Study on a Single Processing Node of the HITACHI SR8000.	NAA	2000	DBLP DOI BibTeX RDF
1	Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt	TriMedia CPU64 Application Development Environment.	ICCD	1999	DBLP DOI BibTeX RDF
1	Randall J. Fisher, Henry G. Dietz	The Scc Compiler: SWARing at MMX 3DNow!	LCPC	1999	DBLP DOI BibTeX RDF
1	José Carlos Alves, José Silva Matos	RVC - A Reconfigurable Coprocessor for Vector Processing Applications.	FCCM	1998	DBLP DOI BibTeX RDF
1	Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto	Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF
1	Damianos G. Karakos, Panos E. Trahanias	Generalized multichannel image-filtering structures.	IEEE Transactions on Image Processing	1997	DBLP DOI BibTeX RDF
1	Jacques Savoy	An Extended Vector-Processing Scheme for Searching Information in Hypertext Systems.	Inf. Process. Manage.	1996	DBLP DOI BibTeX RDF
1	Tiarajú Asmuz Diverio, Ursula A. L. Fernandes, Dalcidio Moraes Claudio	Errors in vector processing and the library libavi.a.	Reliable Computing	1996	DBLP DOI BibTeX RDF