Search results for "verilog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Cherif Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary	Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions.	PEPM	2009	DBLP DOI BibTeX RDF	static array bounds checking, verilog elaboration, verilog wire width consistency, dependent types, dead code elimination
4	David R. Smith	Hardware Synthesis From Encapsulated Verilog Modules.	ASAP	1996	DBLP DOI BibTeX RDF	encapsulated Verilog modules, Verilog writing style, code complexity, automatic inference of control, low level simulation, computational complexity, logic design, inference mechanisms, hardware description languages, hardware synthesis, control points, clock cycle
3	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
3	Huibiao Zhu, Jifeng He, Jonathan P. Bowen	From algebraic semantics to denotational semantics for Verilog.	ISSE	2008	DBLP DOI BibTeX RDF	Unifying theories of programming, Denotational semantics, Semantic relating, Verilog, Algebraic semantics
3	Ravi Surepeddi	System Verilog for Quality of Results (QoR).	ISQED	2008	DBLP DOI BibTeX RDF	System Verilog Design Quality Results
3	Jennifer Gillenwater, Gregory Malecha, Cherif Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'Leary	Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability.	PEPM	2008	DBLP DOI BibTeX RDF	statically typed two-level languages, synthesizability, verilog elaboration, code generation, hardware description languages
3	Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau	Understanding bug fix patterns in verilog.	MSR	2008	DBLP DOI BibTeX RDF	error classification, VHDL, verilog
3	Shengchao Qin, Wei-Ngan Chin, Jifeng He, Zongyan Qiu	From Statecharts to Verilog: a formal approach to hardware/software co-specification.	ISSE	2006	DBLP DOI BibTeX RDF	Operational semantics, Statecharts, Hardware/software partitioning, Homomorphism, Verilog, Algebraic laws
3	Ulya R. Karpuzcu	Automatic verilog code generation through grammatical evolution.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	automatic code generation, grammatical evolution, verilog
3	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word level predicate abstraction and refinement for verifying RTL verilog.	DAC	2005	DBLP DOI BibTeX RDF	SAT, predicate abstraction, verilog
3	Zaher S. Andraus, Karem A. Sakallah	Automatic abstraction and verification of verilog models.	DAC	2004	DBLP DOI BibTeX RDF	UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog
3	Arash Saifhashemi, Hossein Pedram	Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.	DAC	2003	DBLP DOI BibTeX RDF	CHP, PLI, CSP, asynchronous circuits, channel, verilog
3	Shengchao Qin, Wei-Ngan Chin	Mapping Statecharts to Verilog for Hardware/Software Co-specification.	FME	2003	DBLP DOI BibTeX RDF	operational semantics, Statecharts, homomorphism, Verilog
2	Matthias Raffelsieper, Mohammad Reza Mousavi, Jan-Willem Roorda, Chris W. H. Strolenberg, Hans Zantema	Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models.	FMICS	2009	DBLP DOI BibTeX RDF
2	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
2	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Ariana Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
2	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Bernhard Peischl, Naveed Riaz, Franz Wotawa	Advances in Automated Source-Level Debugging of Verilog Designs.	New Challenges in Applied Intelligence Technologies	2008	DBLP DOI BibTeX RDF	debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging
2	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
2	Lijun Li, Carl Tropper	A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation.	ICPP	2008	DBLP DOI BibTeX RDF
2	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Christian Haufe, Frank Rogin	Ad-Hoc Translations to Close Verilog Semantics Gap.	DDECS	2008	DBLP DOI BibTeX RDF
2	Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka	Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.	DDECS	2008	DBLP DOI BibTeX RDF
2	Clifford E. Cummings	SystemVerilog implicit port enhancements accelerate system design & verification.	DAC	2008	DBLP DOI BibTeX RDF	*, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog
2	Gaurav Singh, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
2	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	VCEGAR: Verilog CounterExample Guided Abstraction Refinement.	TACAS	2007	DBLP DOI BibTeX RDF
2	Lijun Li, Carl Tropper	A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation.	PADS	2007	DBLP DOI BibTeX RDF
2	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
2	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	STTT	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
2	Junjun Li, S. Joshi, R. Barnes, E. Rosenbaum	Compact modeling of on-chip ESD protection devices using Verilog-A.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti	Synthesis of system verilog assertions.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
2	Ming-Ta Hsieh, Gerald E. Sobelman	Modeling and verification of high-speed wired links with Verilog-AMS.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Huibiao Zhu, Jifeng He, Jonathan P. Bowen	From Algebraic Semantics to Denotational Semantics for Verilog.	ICECCS	2006	DBLP DOI BibTeX RDF
2	François Pêcheux, Christophe Lallement, Alain Vachoux	VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Tun Li, Yang Guo, Sikun Li, Dan Zhu	Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions.	MICAI	2005	DBLP DOI BibTeX RDF
2	Tun Li, Yang Guo, Sikun Li, GongJie Liu	Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming.	ATVA	2005	DBLP DOI BibTeX RDF
2	Choudhury A. Rahman, Wael M. Badawy	A quarter pel full search block motion estimation architecture for H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
2	Youngsun Han, Seon Kim, Chulwoo Kim	Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing.	ICESS	2005	DBLP DOI BibTeX RDF	Java, FPGA, compiler, Reconfigurable computing, Verilog
2	Li Shen 0002	VFSim: Concurrent Fault Simulation at Register Transfer Level.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
2	Rishiyur S. Nikhil	Bluespec System Verilog: efficient, correct RTL from high level specifications.	MEMOCODE	2004	DBLP DOI BibTeX RDF
2	Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin	An Automatic Mapping from Statecharts to Verilog.	ICTAC	2004	DBLP DOI BibTeX RDF
2	Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo	A Temporal Assertion Extension to Verilog.	ATVA	2004	DBLP DOI BibTeX RDF	temporal assertion, verification, PSL
2	Tun Li, Yang Guo, Sikun Li, FuJiang Ao, GongJie Li	Parallel verilog simulation: architecture and circuit partition.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Tun Li, Yang Guo, Sikun Li	Design and Implementation of a Parallel Verilog Simulator: PVSim.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Tom Fitzpatric	System Verilog for VHDL Users.	DATE	2004	DBLP DOI BibTeX RDF
2	Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev	An Asynchronous Synthesis Toolset Using Verilog.	DATE	2004	DBLP DOI BibTeX RDF
2	Jun Wang, Carl Tropper	Nicarus: A Distributed Verilog Compiler.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
2	Daniel Kroening, Edmund M. Clarke	Checking consistency of C and Verilog using predicate abstraction and induction.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Li Yongjian, Jifeng He	Towards a Theory of Bisimulation for a Fragment of Verilog.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Edmund M. Clarke, Daniel Kroening, Karen Yorav	Behavioral consistency of C and verilog programs using bounded model checking.	DAC	2003	DBLP DOI BibTeX RDF	ANSI-C, equivalence checking, verilog
2	Lijun Li, Hai Huang, Carl Tropper	DVS: An Object-Oriented Framework for Distributed Verilog Simulation.	PADS	2003	DBLP DOI BibTeX RDF
2	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.	ISPDC	2003	DBLP DOI BibTeX RDF
2	Monte Mar, Bert Sullam	Modeling and verification of a programmable mixed-signal device using Verilog.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Huibiao Zhu, Jonathan P. Bowen, Jifeng He	Soundness, Completeness and Non-redundancy of Operational Semantics for Verilog Based on Denotational Semantics.	ICFEM	2002	DBLP DOI BibTeX RDF
2	Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang	Hardware/Software Partitioning in Verilog.	ICFEM	2002	DBLP DOI BibTeX RDF
2	Jifeng He	An Algebraic Approach to the VERILOG Programming.	10th Anniversary Colloquium of UNU/IIST	2002	DBLP DOI BibTeX RDF
2	Kartik Mohanram, C. V. Krishna, Nur A. Touba	A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
2	Jordan Dimitrov	Operational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
2	Huibiao Zhu, Jonathan P. Bowen, Jifeng He	Deriving Operational Semantics from Denotational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
2	Huibiao Zhu, Jonathan P. Bowen, Jifeng He	From Operational Semantics to Denotational Semantics for Verilog.	CHARME	2001	DBLP DOI BibTeX RDF
2	Jonathan P. Bowen, Jifeng He, Qiwen Xu	An Animatable Operational Semantics of the Verilog Hardware Description Language. (PDF / PS)	ICFEM	2000	DBLP DOI BibTeX RDF
2	Alexander Glasmacher, Kai Woska	Design and Implementation of an XC6216 FPGA Model in Verilog.	FPL	2000	DBLP DOI BibTeX RDF
2	David J. Greaves	A Verilog to C Compiler. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
2	Gordon J. Pace	The Semantics of Verilog Using Transition System Combinators.	FMCAD	2000	DBLP DOI BibTeX RDF
2	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
2	Jonathan P. Bowen	Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language.	IFM	2000	DBLP DOI BibTeX RDF
2	James Jennings, Eric Beuscher	Verischemelog: Verilog embedded in Scheme.	DSL	1999	DBLP DOI BibTeX RDF
2	Gerardo Schneider, Qiwen Xu	Towards a Formal Semantics of Verilog Using Duration Calculus.	FTRTFT	1998	DBLP DOI BibTeX RDF
2	Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT.	DAC	1997	DBLP DOI BibTeX RDF
2	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
2	Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
2	Nam Ling, Rajesh Advani	Architecture of a fast motion estimator for MPEG video coding.	ISPAN	1996	DBLP DOI BibTeX RDF	fast motion estimator, MPEG video coding, 2-D log search, MPEG2 video, motion estimation, motion estimator, video coding, systolic arrays, motion vector, Verilog, Synopsys
2	M. E. Waite, T. J. Reynolds, F. Z. Ieromnimon	Parallel Graph Reduction with the PACE Architecture.	PDP	1996	DBLP DOI BibTeX RDF	parallel graph reduction, PACE architecture, graph reduction model, basic replicable node, prototype version, Verilog description, C simulator, parallel programming, graph theory, parallel architectures, virtual machines, distributed memory systems, parallel execution, distributed memory multiprocessor
2	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
2	Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby	Three Decades of HDLs: Part II, Conlan Through Verilog.	IEEE Design & Test of Computers	1992	DBLP DOI BibTeX RDF
1	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson	The VTR project: architecture and CAD for FPGAs from verilog to routing.	FPGA	2012	DBLP DOI BibTeX RDF
1	Cherif Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary	Static consistency checking for Verilog wire interconnects - Using dependent types to check the sanity of Verilog descriptions.	Higher-Order and Symbolic Computation	2011	DBLP DOI BibTeX RDF
1	Jun Ye, Qingping Tan, Tun Li, GuoRong Cao	FeatureVerilog: Extending Verilog to Support Feature-Oriented Programming.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo	Verilog-A modeling of SPAD statistical phenomena.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Junbeom Yoo, Jong-Hoon Lee, Sehun Jeong, Sung Deok Cha	FBDtoVerilog: A Vendor-Independent Translation from FBDs into Verilog Programs.	SEKE	2011	DBLP BibTeX RDF
1	Yosi Ben-Asher, Nadav Rotem, Eddie Shochat	Finding the best compromise in compiling compound loops to Verilog.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Patrick O'Neil Meredith, Michael Katelman, José Meseguer, Grigore Rosu	A formal executable semantics of Verilog.	MEMOCODE	2010	DBLP DOI BibTeX RDF
1	Adam Duley, Chris Spandikow, Miryung Kim	A program differencing algorithm for verilog HDL.	ASE	2010	DBLP DOI BibTeX RDF
1	Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes	Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.	UKSim	2010	DBLP DOI BibTeX RDF
1	Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon	Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research.	FCCM	2010	DBLP DOI BibTeX RDF
1	Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg	Checking and deriving module paths in Verilog cell library descriptions.	DATE	2010	DBLP BibTeX RDF
1	Seyed-Nematollah Ahmadian, Seyed-Ghassem Miremadi	Fault injection in mixed-signal environment using behavioral fault modeling in Verilog-A.	BMAS	2010	DBLP DOI BibTeX RDF
1	ByongChan Lim, Jaeha Kim, Mark A. Horowitz	An efficient test vector generation for checking analog/mixed-signal functional models.	DAC	2010	DBLP DOI BibTeX RDF	linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits
1	Sina Meraji, Wei Zhang 0034, Carl Tropper	Brief announcement: a reinforcement learning approach for dynamic load-balancing of parallel digital logic simulation.	SPAA	2010	DBLP DOI BibTeX RDF	digital logic simulation, reinforcement learning, dynamic load-balancing, time warp, verilog
1	Yun-Hung Liaw, Shih-Hao Hung, Chia-Heng Tu	V2X: An Automated Tool for Building SystemC-Based Simulation Environments in Designing Multicore Systems-on-Chips.	ISPA	2010	DBLP DOI BibTeX RDF	Systems-on-Chips, Multicore, translator, SystemC, Verilog, system-level simulation
1	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
1	Marc Schlickling, Markus Pister	Semi-automatic derivation of timing models for WCET analysis.	LCTES	2010	DBLP DOI BibTeX RDF	vhdl, worst-case execution time, hard real-time
1	Lijun Li, Carl Tropper	A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation.	Simulation	2009	DBLP DOI BibTeX RDF
1	Zhang Zhen, Zhang Hui	The Hardware Interface Design In SoC with Verilog Language.	SSME	2009	DBLP DOI BibTeX RDF
1	Matthias Raffelsieper, Jan-Willem Roorda, Mohammad Reza Mousavi	Model Checking Verilog Descriptions of Cell Libraries.	ACSD	2009	DBLP DOI BibTeX RDF
1	Sina Meraji, Wei Zhang 0034, Carl Tropper	On the Scalability of Parallel Verilog Simulation.	ICPP	2009	DBLP DOI BibTeX RDF
1	Bernhard Peischl, Naveed Riaz, Franz Wotawa	Employing Test Suites for Verilog Fault Localization.	CAEPIA	2009	DBLP DOI BibTeX RDF
1	Purvi D. Mulani	SoC Level Verification Using System Verilog.	ICETET	2009	DBLP DOI BibTeX RDF