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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 6 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | André van Schaik, Eric Fragnière |
Pseudo-voltage domain implementation of a 2-dimensional silicon cochlea.  |
ISCAS  |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Tom Van Breussegem, Michiel Steyaert |
Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS.  |
J. Solid-State Circuits  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dynamic voltage domain assignment technique for low power performance manageable cell based design.  |
ASP-DAC  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser |
Multiple clock and voltage domains for chip multi processors.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
clock domains, voltage domain, power management, DVFS, chip multi processor |
| 1 | Laurent Souef, Christophe Eychenne, Emmanuel Alie |
Architecture for Testing Multi-Voltage Domain SOC.  |
ITC  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam |
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Shuilong Huang, Huainan Ma, Zhihua Wang |
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer.  |
DATE  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Jaeha Kim, Kevin D. Jones, Mark A. Horowitz |
Variable domain transformation for linear PAC analysis of mixed-signal systems.  |
ICCAD  |
2007 |
DBLP DOI BibTeX RDF |
PAC analysis, domain transformation, linear analysis, simulation |
| 1 | Nevine AbouGhazaleh, Alexandre Peixoto Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem |
Integrated CPU and l2 cache voltage scaling using machine learning.  |
LCTES  |
2007 |
DBLP DOI BibTeX RDF |
integrated DVS policy, machine learning, power management, multiple clock domains |
| 1 | Ivo Lattenberg, Kamil Vrba, David Kubanek |
Signal Processing for High-Speed Data Communication Using Pure Current Mode Filters.  |
ICN  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Hassan O. Elwan, Mohammed Ismail |
Low Voltage Low power CMOS AGC circuit for wireless communication.  |
Great Lakes Symposium on VLSI  |
1998 |
DBLP DOI BibTeX RDF |
Automatic gain control, Variable gain amplifier, dB-Linear |
Displaying result #1 - #11 of 11 (100 per page; Change: )
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